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ORCIDHiroshi Sasaki 0001
Person information
- affiliation: Tokyo Institute of Technology, Japan
- affiliation (former): Columbia University, NY, USA
- affiliation (former): Kyushu University
- affiliation (former): The University of Tokyo, Japan
Other persons with the same name
- Hiroshi Sasaki — disambiguation page
- Hiroshi Sasaki 0002 — Kyoto University, Kyoto, Japan (and 1 more)
- Hiroshi Sasaki 0003 — Rikkyo University, Tokyo, Japan
- Hiroshi Sasaki 0004 — Fukui University of Technology, Fukui, Japan
- Hiroshi Sasaki 0005 — Denso IT Laboratory, Inc., Shibuya Shibuya-ku Tokyo, Japan
- Hiroshi Sasaki 0006 — Kanazawa Medical University, Japan
- Hiroshi Sasaki 0007
![[0000-0001-8752-6846]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-8752-6846")
— Osaka University, Graduate School of Frontier Biosciences, Suita, Japan (and 4 more) - Hiroshi Sasaki 0008 — Kokusai Denshin Denwa Company, Research & Development Laboratories, Tokyo, Japan
- Hiroshi Sasaki 0009 — Durham University, UK
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2020 – today
- 2021
[c24]Keisuke Nishimura, Takahiro Ishikawa, Hiroshi Sasaki, Shinpei Kato:
RAPLET: Demystifying Publish/Subscribe Latency for ROS Applications. RTCSA 2021: 41-50
2010 – 2019
- 2019
- [c23]Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad, Koustubha Bhat, Kanad Sinha, Simha Sethumadhavan:
Practical Byte-Granular Memory Blacklisting using Califorms. MICRO 2019: 558-571 - [i2]Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad, Koustubha Bhat, Kanad Sinha, Simha Sethumadhavan:
Practical Byte-Granular Memory Blacklisting using Califorms. CoRR abs/1906.01838 (2019) - 2018
- [j8]Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa:
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs. IEICE Trans. Inf. Syst. 101-D(9): 2247-2257 (2018) - [i1]Aaron Smith, Chris Fensch, Hiroshi Sasaki:
Advances in Heterogeneous Computing from Hardware to Software (NII Shonan Meeting 2018-11). NII Shonan Meet. Rep. 2018 (2018) - 2017
- [j7]Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan:
Heavy Tails in Program Structure. IEEE Comput. Archit. Lett. 16(1): 34-37 (2017) - [j6]Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose:
Mitigating Power Contention: A Scheduling Based Approach. IEEE Comput. Archit. Lett. 16(1): 60-63 (2017) - [j5]Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki:
Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. IEEE Comput. Archit. Lett. 16(2): 111-114 (2017) - [c22]Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan:
Why do programs have heavy tails? IISWC 2017: 135-145 - 2016
- [j4]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. 99-D(12): 2881-2890 (2016) - [c21]Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose:
Characterization and mitigation of power contention across multiprogrammed workloads. IISWC 2016: 55-64 - [c20]Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro:
A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform. MCSoC 2016: 46-52 - [c19]Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa:
Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping. HPGDMP@SC 2016: 17-24 - 2015
- [c18]Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue:
A flexible hardware barrier mechanism for many-core processors. ASP-DAC 2015: 61-68 - [c17]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD 2015: 455-458 - 2014
- [c16]Satoshi Imamura, Hiroshi Sasaki, Koji Inoue, Dimitrios S. Nikolopoulos:
Power-capped DVFS and thread allocation with ANN models on modern NUMA systems. ICCD 2014: 324-331 - [c15]Yuki Abe, Hiroshi Sasaki, Shinpei Kato, Koji Inoue, Masato Edahiro, Martin Peres:
Power and Performance Characterization and Modeling of GPU-Accelerated Systems. IPDPS 2014: 113-122 - 2013
- [c14]Hiroshi Sasaki, Satoshi Imamura, Koji Inoue:
Coordinated power-performance optimization in manycores. PACT 2013: 51-61 - [c13]Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
McRouter: Multicast within a router for high performance network-on-chips. PACT 2013: 319-329 - [c12]Masaaki Kondo, Son Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, Koji Inoue:
SMYLEref: A reference architecture for manycore-processor SoCs. ASP-DAC 2013: 561-564 - [c11]Keitarou Oka, Hiroshi Sasaki, Koji Inoue:
Line sharing cache: Exploring cache capacity with frequent line value locality. ASP-DAC 2013: 669-674 - [c10]Yuki Abe, Hiroshi Sasaki, Shinpei Kato, Koji Inoue, Masato Edahiro, Martin Peres:
Power and performance of GPU-accelerated systems: A closer look. IISWC 2013: 109-110 - [c9]Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops 2013: 842-850 - 2012
- [j3]Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura:
Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. 7(1): 153-160 (2012) - [c8]Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura:
Scalability-based manycore partitioning. PACT 2012: 107-116 - [c7]Yuki Abe, Hiroshi Sasaki, Martin Peres, Koji Inoue, Kazuaki J. Murakami, Shinpei Kato:
Power and Performance Analysis of GPU-Accelerated Systems. HotPower 2012 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [c6]Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki J. Murakami:
Performance evaluation of 3D stacked multi-core processors with temperature consideration. 3DIC 2011: 1-5
2000 – 2009
- 2009
- [j2]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 848-852 (2009) - [c5]Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura:
Power-performance modeling of heterogeneous cluster-based web servers. GRID 2009: 225-231 - [c4]Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Cooperative shared resource access control for low-power chip multiprocessors. ISLPED 2009: 177-182 - 2007
- [j1]Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura:
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. SIGARCH Comput. Archit. News 35(1): 31-38 (2007) - [c3]Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura:
An intra-task dvfs technique based on statistical analysis of hardware events. Conf. Computing Frontiers 2007: 123-130 - 2006
- [c2]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Energy-efficient dynamic instruction scheduling logic through instruction grouping. ISLPED 2006: 43-48 - 2005
- [c1]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura:
Dynamic Instruction Cascading on GALS Microprocessors. PATMOS 2005: 30-39
Coauthor Index
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