default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID8th NorCAS 2022, Oslo, Norway
- Jari Nurmi
, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard:
IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, Norway, October 25-26, 2022. IEEE 2022, ISBN 979-8-3503-4550-6 - Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
GLS Tracing: Gem5-based Low-intrusive Software Tracing. 1-6 - Franz Marcus Schüffny, Stefan Hänzsche, Marc Berthel, Seyed Mohammad Ali Zeinolabedin, Stefan Scholze, Sebastian Höppner, Richard Miru George, Christian Mayr:
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm. 1-5 - Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson, Per Larsson-Edefors:
Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs. 1-6 - Negar Shabanzadeh, Mostafa Jafari Nokandi, Kimmo Rasilainen, Jiangcheng Chen, Sumit Pratap Singh, Aarno Pärssinen, Timo Rahkonen:
A Study of the Effects Limiting the Responsivity of A Broadband THz Power Detector with On-chip Antenna in $0.13\mu \mathrm{m}$ SiGe HBT Technology. 1-5 - Mayank Kabra, Prashanth H. C., Madhav Rao:
Design and Evaluation of Performance-efficient SoC-on-FPGA for Cloud-based Healthcare Applications. 1-6 - Esko Pekkarinen, Mikko Teuho, Timo Hämäläinen:
Python API for Kactus2 IP-XACT tool. 1-5 - Yu-Kai Huang, Saul Rodriguez:
Noise Analysis of Current-Feedback DC-Servo Loop in Current-Balancing Chopper Amplifiers. 1-6 - Maryam Rafati, Seyed Ruhallah Qasemi, Atila Alvandpour:
A Dynamic Range Extension Technique for Pseudo-Resistive Transimpedance Amplifiers Based on Two-Step Conversion. 1-5 - Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh, Kris Gaj:
CRC-Oriented Error Detection Architectures of Post-quantum Cryptography Niederreiter Key Generator on FPGA. 1-7 - Rizwan Tariq Syed, Yanhua Zhao, Markus Ulbricht, Vladica Sark, Milos Krstic:
FPGA-Based Acceleration of Convolutional Neural Network for Gesture Recognition Using mm-Wave FMCW Radar. 1-7 - Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal:
High-level Comparison of Control-Bounded A/D Converters and Continuous- Time Sigma-Delta Modulators. 1-5 - Thomas Mausolf, Frank Herzel, Gunter Fischer:
An Integrated Circuit to Reduce Phase Noise and Spurious Tones in Radar Systems. 1-5 - Christian Lanius, Tobias Gemmeke:
Multi-Function CIM Array for Genome Alignment Applications built with Fully Digital Flow. 1-7 - Siavash Mowlavi, Stavros Giannakopoulos, Lars Svensson:
VCSEL Integrated Circuit Drivers: A Review. 1-7 - Xinyi Ge, Yong Chen, Lin Wang, Nan Qi, Pui-In Mak, Rui Paulo Martins:
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. 1-7 - Sebastian Birke, Bjoern Hartmann, Dominik Auras, Markus Wloka, Gerd Ascheid, Rainer Leupers:
Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications. 1-7 - Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano:
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. 1-7 - Johnson Loh, Tobias Gemmeke:
Dataflow Optimizations in a Sub-uW Data-Driven TCN Accelerator for Continuous ECG Monitoring. 1-7 - Mohammad Riazati, Masoud Daneshtalab, Mikael Sjödin, Björn Lisper:
DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator. 1-6 - Qirui Hua, Laura Amalie Rytoft, Ben Klauman KrØyer, Ole Rahbek, SØren Vedding Kold, Ming Shen:
Design and In-Vivo Test of Battery-Free Implantable Temperature Sensor Based on Magnetic Resonant Wireless Power Transfer. 1-6 - Victor Aberg, Han Zhou, Christian Fager, Lars Svensson:
RF PA Predistortion using Non-Linear RF-DACs. 1-6 - Syed Anas Alam, Jakob Furbo Enevoldsen, Andreas Alkjaer Eriksen, Niels William Hartmann, Ulrik Helk, Jphirgen Kragh Jakobsen, Christa Skytte Jensen, Nicolai Dyre Bülow Jespersen, Karl Herman Krause, Mads Rumle Nordstrphim, Tjark Petersen, Luca Pezzarossa, Simon Winther Rasmussen, Martin Schoeberl, Jonas Ingerslev Sphirensen:
Open-Source Chip Design in Academic Education. 1-6 - Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Vishnu Unnikrishnan, Vesa Lampu, Guixian Xu, Lauri Anttila, Kari Stadius, Marko Kosunen, Jussi Ryynänen:
Reconfigurable Signal Processing and DSP Hardware Generator for 5G Transmitters. 1-7 - Baktash Behmanesh, Joachim Rodrigues, Henrik Sjöland:
An 88% fractional bandwidth reconfigurable power amplifier for NB-IoT and LTE-M in 22 nm CMOS FDSOI. 1-4 - Safdar Mahmood, Stefan Scharoba, Jonas Schorlemer, Christian Schulz, Michael Hübner, Marc Reichenbach:
Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs. 1-7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-29 20:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
