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ORCIDDmitri Mihhailov
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2020 – today
- 2024
[c15]Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee:
Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. NorCAS 2024: 1-7- [i2]Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee:
Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. CoRR abs/2410.20430 (2024) - 2022
- [i1]Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman:
HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. CoRR abs/2212.04374 (2022)
2010 – 2019
- 2013
- [c14]Dmitri Mihhailov, Artjem Rjabov, Valery Sklyarov
, Iouliia Skliarova, Alexander Sudnitson:
Optimization of address-based data sorting unit with external memory support. CompSysTech 2013: 83-90 - [c13]Valery Sklyarov, Iouliia Skliarova, Margus Kruus, Dmitri Mihhailov, Alexander Sudnitson:
Address-based data processing over N-ary trees. EUROCON 2013: 1790-1797 - [c12]Dmitri Mihhailov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova:
Implementation of address-based data sorting on different FPGA platforms. EWDTS 2013: 1-4 - 2012
- [c11]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Performance evaluation for FPGA-based processing of tree-like structures. ICECS 2012: 217-220 - 2011
- [c10]Dmitri Mihhailov, Margus Kruus, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Recursion and hierarchy in digital design and prototyping: a case study. CompSysTech 2011: 45-50 - [c9]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
High-performance hardware accelerators for sorting and managing priorities. DDECS 2011: 313-318 - [c8]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Implementation in FPGA of Address-Based Data Sorting. FPL 2011: 405-410 - [c7]Maksim Jenihhin, Maksim Gorev, Vadim Pesonen, Dmitri Mihhailov, Peeter Ellervee, Hiie Hinrikus, Maie Bachmann, Jaanus Lass:
EEG Analyzer prototype based on FPGA. ISPA 2011: 101-106 - 2010
- [c6]Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus:
Advanced topics of FSM design using FPGA educational boards and web-based tools. EWDTS 2010: 514-517 - [c5]Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Application-specific hardware accelerator for implementing recursive sorting algorithms. FPT 2010: 269-272 - [c4]Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Parallel FPGA-Based Implementation of Recursive Sorting Algorithms. ReConFig 2010: 121-126 - [c3]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. ReConFig 2010: 436-441
2000 – 2009
- 2009
- [c2]Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus, Konstantin Tarletski:
FSM decomposition with application to FPGA synthesis. CompSysTech 2009: 74 - 2008
- [c1]Dmitri Mihhailov, Margus Kruus, Alexander Sudnitson:
FPGA platform based digital design education. CompSysTech 2008: 53
Coauthor Index
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