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ORCIDValery Sklyarov
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- affiliation: Instituto de Engenharia Electronica e Telematica de Aveiro, Portugal
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2010 – 2019
- 2019
[b1]Iouliia Skliarova, Valery Sklyarov:
FPGA-BASED Hardware Accelerators. Lecture Notes in Electrical Engineering 566, Springer 2019, ISBN 978-3-030-20720-5, pp. 1-241- 2017
- [j14]Valery Sklyarov, Iouliia Skliarova
:
Data processing in the firmware systems for logic control based on search networks. Autom. Remote. Control. 78(1): 100-112 (2017) - [c55]Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus:
Reconfigurable systems in engineering education: Best practices and future trends. EDUCON 2017: 1084-1088 - [c54]Artjem Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
RAM-based mergers for data sort and frequent item computation. MIPRO 2017: 176-181 - 2016
- [j13]Valery Sklyarov, Iouliia Skliarova, Artjem Rjabov, Alexander Sudnitson:
Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems. Int. J. Comput. Commun. Control 11(1): 126-141 (2016) - [j12]Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva:
On-Chip Reconfigurable Hardware Accelerators for Popcount Computations. Int. J. Reconfigurable Comput. 2016: 8972065:1-8972065:11 (2016) - 2015
- [j11]Valery Sklyarov, Iouliia Skliarova:
Design and implementation of counting networks. Computing 97(6): 557-577 (2015) - [j10]João Paulo Sá da Silva, Valery Sklyarov, Iouliia Skliarova:
Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip. IEEE Embed. Syst. Lett. 7(1): 31-34 (2015) - [j9]Valery Sklyarov, Iouliia Skliarova:
Multi-core DSP-based Vector Set Bits Counters/Comparators. J. Signal Process. Syst. 80(3): 309-322 (2015) - [c53]Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva, Alexander Sudnitson:
Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip. DSD 2015: 345-352 - [c52]Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson, Margus Kruus:
FPGA-based time and cost effective Hamming weight comparators for binary vectors. EUROCON 2015: 1-6 - [c51]Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus:
Integration of high-level synthesis to the courses on reconfigurable digital systems. MIPRO 2015: 166-171 - 2014
- [j8]Valery Sklyarov, Iouliia Skliarova:
High-performance implementation of regular and easily scalable sorting networks on an FPGA. Microprocess. Microsystems 38(5): 470-484 (2014) - [j7]Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
FPGA-based Accelerators for Parallel Data Sort. Appl. Comput. Syst. 16(1): 53 (2014) - [c50]Valery Sklyarov, Iouliia Skliarova, João Paulo Sá da Silva, Alexander Sudnitson:
Design space exploration in multi-level computing systems. CompSysTech 2014: 40-47 - [c49]Iouliia Skliarova, Valery Sklyarov, Alexander Sudnitson, Margus Kruus:
Teaching FPGA-based systems. EDUCON 2014: 460-469 - 2013
- [j6]Valery Sklyarov, Iouliia Skliarova:
Hardware implementations of software programs based on hierarchical finite state machine models. Comput. Electr. Eng. 39(7): 2145-2160 (2013) - [c48]Dmitri Mihhailov, Artjem Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Optimization of address-based data sorting unit with external memory support. CompSysTech 2013: 83-90 - [c47]Valery Sklyarov, Iouliia Skliarova, Margus Kruus, Dmitri Mihhailov, Alexander Sudnitson:
Address-based data processing over N-ary trees. EUROCON 2013: 1790-1797 - [c46]Dmitri Mihhailov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova:
Implementation of address-based data sorting on different FPGA platforms. EWDTS 2013: 1-4 - [c45]Valery Sklyarov, Iouliia Skliarova, Artjem Rjabov, Alexander Sudnitson:
Implementation of parallel operations over streams in extensible processing platforms. MWSCAS 2013: 852-855 - 2012
- [c44]Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Methodology and international collaboration in teaching reconfigurable systems. EDUCON 2012: 1-10 - [c43]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Performance evaluation for FPGA-based processing of tree-like structures. ICECS 2012: 217-220 - 2011
- [c42]Dmitri Mihhailov, Margus Kruus, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Recursion and hierarchy in digital design and prototyping: a case study. CompSysTech 2011: 45-50 - [c41]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
High-performance hardware accelerators for sorting and managing priorities. DDECS 2011: 313-318 - [c40]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Implementation in FPGA of Address-Based Data Sorting. FPL 2011: 405-410 - 2010
- [c39]Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Application-specific hardware accelerator for implementing recursive sorting algorithms. FPT 2010: 269-272 - [c38]Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson:
Parallel FPGA-Based Implementation of Recursive Sorting Algorithms. ReConFig 2010: 121-126 - [c37]Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson:
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. ReConFig 2010: 436-441
2000 – 2009
- 2009
- [c36]Iouliia Skliarova, Valery Sklyarov:
Recursion in reconfigurable computing: A survey of implementation approaches. FPL 2009: 224-229 - 2008
- [c35]Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Manuel Almeida:
Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems. VLSI Design 2008: 85-90 - [c34]Iouliia Skliarova, Valery Sklyarov:
Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware. VLSI Design 2008: 255-260 - 2007
- [c33]Valery Sklyarov, Iouliia Skliarova:
Encoding Algorithms for Logic Synthesis. AICCSA 2007: 359-366 - [c32]Iouliia Skliarova, Valery Sklyarov:
Software/Configware Implementation of Combinatorial Algorithms. AICCSA 2007: 539-546 - [c31]Valery Sklyarov, Iouliia Skliarova:
Reuse Technique in Hardware Design. IRI 2007: 36-41 - [c30]Valery Sklyarov, Iouliia Skliarova, Manuel Almeida, Bruno Figueiredo Pimentel:
A prototyping system for mobile devices. IWCMC 2007: 505-510 - 2006
- [c29]Valery Sklyarov, Iouliia Skliarova:
Recursive and Iterative Algorithms for N-ary Search Problems. IFIP PPAI 2006: 81-90 - [c28]Valery Sklyarov, Iouliia Skliarova:
Evolutionary Algorithm for State Encoding. IFIP AI 2006: 227-236 - [c27]Valery Sklyarov, Iouliia Skliarova:
E-learning Tools and Web-resources for Teaching Reconfigurable Systems. Education for the 21st Century 2006: 215-224 - [c26]Valery Sklyarov, Iouliia Skliarova:
Reconfigurable Systems and their Influence on Mobile and Multimedia Applications. MoMM 2006: 7-8 - [c25]Valery Sklyarov, Iouliia Skliarova:
Multimedia Tools for Teaching Reconfigurable Systems. MoMM 2006: 211-220 - 2005
- [j5]Valery Sklyarov, Iouliia Skliarova:
Teaching reconfigurable systems: methods, tools, tutorials, and projects. IEEE Trans. Educ. 48(2): 290-300 (2005) - [c24]Arnaldo S. R. Oliveira, Valery Sklyarov, António de Brito Ferrari:
ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications. DSD 2005: 484-491 - [c23]Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel:
FPGA-based implementation and comparison of recursive and iterative algorithms. FPL 2005: 235-240 - 2004
- [j4]Valery Sklyarov:
FPGA-based implementation of recursive algorithms. Microprocess. Microsystems 28(5-6): 197-211 (2004) - [c22]Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Joel Arrais:
Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers. FPL 2004: 922-926 - 2003
- [c21]Valery Sklyarov, Iouliia Skliarova:
Design of Digital Circuits on the Basis of Hardware Templates. Embedded Systems and Applications 2003: 56-62 - [c20]Valery Sklyarov, Iouliia Skliarova, Arnaldo S. R. Oliveira, António de Brito Ferrari:
A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. DSD 2003: 222-229 - [c19]Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida:
Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. DSD 2003: 255-263 - [c18]Valery Sklyarov, Iouliia Skliarova:
Architecture of a Reconfigurable Processor for Implementing Search Algorithm over Discrete Matrices. Engineering of Reconfigurable Systems and Algorithms 2003: 127-133 - [c17]Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida:
High-Level Design Tools for FPGA-Based Combinatorial Accelerators. FPL 2003: 976-979 - [c16]Valery Sklyarov, Iouliia Skliarova:
Reconfigurable Systems in Education. FPL 2003: 1020-1023 - 2002
- [j3]Valery Sklyarov:
Reconfigurable models of finite state machines and their implementation in FPGAs. J. Syst. Archit. 47(14-15): 1043-1064 (2002) - [j2]Valery Sklyarov:
Hardware/software modeling of FPGA-based systems. Parallel Algorithms Appl. 17(1): 19-39 (2002) - [c15]Valery Sklyarov:
An Evolutionary Algorithm for the Synthesis of RAM-Based FSMs. IEA/AIE 2002: 108-118 - 2000
- [c14]Valery Sklyarov:
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. FPL 2000: 718-728 - [c13]Arkadij Zakrevskij, Valery Sklyarov:
The Specification and Design of Parallel Logical Control Devices. PDPTA 2000 - [c12]Valery Sklyarov:
Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAs. SBCCI 2000: 353-358
1990 – 1999
- 1999
- [j1]Valery Sklyarov:
Hierarchical finite-state machines and their use for digital control. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 222-228 (1999) - [c11]Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari:
Development System for FPGA-Based Digital Circuits. FCCM 1999: 266-267 - [c10]Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Konstantin Kondratjuk, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari:
FPGA-Targeted Development System for Embedded Applications. FPGA 1999: 248 - [c9]Arnaldo S. R. Oliveira, Andreia Melo, Valery Sklyarov:
Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs. FPL 1999: 313-322 - [c8]Arnaldo S. R. Oliveira, Valery Sklyarov:
Implementation of virtual control circuits in dynamically reconfigurable FPGAs. ICECS 1999: 217-220 - [c7]Nuno Lau, Valery Sklyarov:
Dynamically Reconfigurable Implementation of Control Circuits. VLSI 1999: 137-148 - [c6]Valery Sklyarov:
Graphical Description and Hardware Implementation of Parallel Control Algorithms. PDPTA 1999: 1390-1396 - 1998
- [c5]Valery Sklyarov, Nuno Lau, Ricardo Sal Monteiro, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk:
Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs. EUROMICRO 1998: 10200-10203 - [c4]Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk:
Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs. FPL 1998: 19-28 - [c3]Valery Sklyarov, António de Brito Ferrari:
Design and implementation of control circuits based on dynamically reconfigurable FPGA. ICECS 1998: 527-530 - [c2]Valery Sklyarov, Nuno Lau, Arnaldo S. R. Oliveira, Andreia Melo, Konstantin Kondratjuk, António de Brito Ferrari, Ricardo Sal Monteiro, Iouliia Skliarova:
Synthesis Tools and Design Environment for Dynamically Reconfigurable FPGAs. SBCCI 1998: 46-50 - [c1]Valery Sklyarov:
Logic Synthesis of Reconfigurable Control Circuits based on Mutually Exclusive Reprogrammable Elements. SBCCI 1998: 221-225
Coauthor Index
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