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Eros Camacho-Ruiz
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2020 – today
- 2024
- [c11]Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox:
Cryptographic Security Through a Hardware Root of Trust. ARC 2024: 106-119 - [c10]Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox:
Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems. NorCAS 2024: 1-7 - 2023
- [j4]Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Santiago Sánchez-Solano, Piedad Brox:
Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems. Cryptogr. 7(2): 29 (2023) - [c9]Eros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Piedad Brox:
A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem. DCIS 2023: 1-6 - [c8]Eros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Piedad Brox:
A complete SHA-3 hardware library based on a high efficiency Keccak design. NorCAS 2023: 1-7 - [c7]Eros Camacho-Ruiz, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Design considerations for a CMOS 65-nm RTN-based PUF. SMACD 2023: 1-4 - [c6]F. J. Rubio-Barbero, Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF. SMACD 2023: 1-4 - 2022
- [j3]Macarena C. Martínez-Rodríguez, Luis F. Rojas-Muñoz, Eros Camacho-Ruiz, Santiago Sánchez-Solano, Piedad Brox:
Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems. Cryptogr. 6(4): 51 (2022) - [j2]Santiago Sánchez-Solano, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox:
Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems. Sensors 22(5): 2057 (2022) - [c5]Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Piedad Brox, Francisco V. Fernández:
A novel Physical Unclonable Function using RTN. ISCAS 2022: 160-164 - [c4]Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
High-level design of a novel PUF based on RTN. SMACD 2022: 1-4 - [c3]Eros Camacho-Ruiz, Andrés Santana-Andreo, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF. SMACD 2022: 1-4 - 2021
- [j1]Eros Camacho-Ruiz, Santiago Sánchez-Solano, Piedad Brox, Macarena C. Martínez-Rodríguez:
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm. ACM J. Emerg. Technol. Comput. Syst. 17(3): 35:1-35:16 (2021) - [c2]Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Santiago Sánchez-Solano, Piedad Brox:
Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs. DCIS 2021: 1-6 - 2020
- [c1]Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Santiago Sánchez-Solano, Piedad Brox:
Accelerating the Development of NTRU Algorithm on Embedded Systems. DCIS 2020: 1-6
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last updated on 2024-11-27 21:25 CET by the dblp team
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