"Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency ..."

Weihuang Wang et al. (2009)

> Home

Details and statistics

DOI: 10.1166/JOLPE.2009.1031

access: closed

type: Journal Article

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jolpe/WangKGC09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jolpe/WangKGC09
Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi:
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. J. Low Power Electron. 5(3): 303-312 (2009)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.