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James Sage

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2010 – 2019

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2014
[c5]
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  dblp key:
  - conf/itc/KellerCFCGSSPS14
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  - https://dblp.org/rec/conf/itc/KellerCFCGSSPS14
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen:
Efficient testing of hierarchical core-based SOCs. ITC 2014: 1-10

2000 – 2009

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2008
[c4]
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  - conf/itc/ChickermaneGSYC08
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  - https://dblp.org/rec/conf/itc/ChickermaneGSYC08
Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula:
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC 2008: 1-10
2007
[c3]
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  - conf/itc/BhargavaMS07
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Gaurav Bhargava, Dale Meehl, James Sage:
Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns. ITC 2007: 1-7
2000
[c2]
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  - conf/iccd/CogswellPST00
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Michael Cogswell, Don Pearl, James Sage, Alan Troidl:
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. ICCD 2000: 473-478
[c1]
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Michael Cogswell, Don Pearl, James Sage, Alan Troidl:
Test structure verification of logical BIST: problems and solutions. ITC 2000: 123-130

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