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ORCIDITC 2013: Anaheim, CA, USA
- 2013 IEEE International Test Conference, ITC 2013, Anaheim, CA, USA, September 6-13, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-0859-2
- Gordon W. Roberts, Rob Aitken:
Welcome message. 1 - Harry H. Chen, Roger Hsu, PaulYoung Yang, J. J. Shyr:
Predicting system-level test and in-field customer failures using data mining. 1-10 - Nik Sumikawa, Li-C. Wang
, Magdy S. Abadir:
A pattern mining framework for inter-wafer abnormality analysis. 1-10 - Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang:
On the generation of compact test sets. 1-10 - Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. 1-10 - Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) scan chain stitching. 1-10 - Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel:
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. 1-10 - Daniel Chow, Masashi Shimanouchi, Mike Peng Li:
Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities. 1-8 - Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri:
VLSI testing based security metric for IC camouflaging. 1-4 - Joshua Ferry:
FPGA-based universal embedded digital instrument. 1-9 - Yanjing Li, Eric Cheng, Samy Makar, Subhasish Mitra:
Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study. 1-10 - Kun-Han Tsai, Shuo Sheng:
Design rule check on the clock gating logic for testability and beyond. 1-8 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. 1-10 - Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu:
AgentDiag: An agent-assisted diagnostic framework for board-level functional failures. 1-8 - Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A novel test structure for measuring the threshold voltage variance in MOSFETs. 1-8 - Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Representative critical-path selection for aging-induced delay monitoring. 1-10 - Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl:
Differential scan-path: A novel solution for secure design-for-testability. 1-9 - Senthil Arasu, Mehrdad Nourani, John M. Carulli, Kenneth M. Butler, Vijay Reddy:
A design-for-reliability approach based on grading library cells for aging effects. 1-7 - Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles:
EDT bandwidth management - Practical scenarios for large SoC designs. 1-10 - Kwang-Hyun Kim:
Keynote address tuesday: Challenges in mobile devices: Process, design and manufacturing. 8 - Jennifer Dworak, Al Crouch, John C. Potter, Adam Zygmontowicz, Micah Thornton:
Don't forget to lock your SIB: Hiding instruments using P16871. 1-10 - Amirali Ghofrani, Miguel Angel Lastras-Montaño, Kwang-Ting Cheng:
Towards data reliable crossbar-based memristive memories. 1-10 - Wei Gao, Chris Liu:
Performance enhancement of a WCDMA/HSDPA+ receiver via minimizing error vector magnitude. 1-7 - Zoe Conroy, Alfred L. Crouch:
BA-BIST: Board test from inside the IC out. 1 - Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir:
True non-intrusive sensors for RF built-in test. 1-10 - Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj:
SmartScan - Hierarchical test compression for pin-limited low power designs. 1-9 - Z. Yu, D. Chen:
Best paper award winners. 4 - Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. 1-8 - Suraj Sindia, Vishwani D. Agrawal:
High sensitivity test signatures for unconventional analog circuit test paradigms. 1-10 - Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai:
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. 1-8 - Siva Sudani, Li Xu, Degang Chen:
Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clipping. 1-10 - Timothy Lyons, George Conner, John Aslanian, Shawn Sullivan:
The implementation and application of a protocol aware architecture. 1-10 - Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang:
A circular pipeline processing based deterministic parallel test pattern generator. 1-8 - Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen:
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs. 1-10 - Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn:
Two-level compression through selective reseeding. 1-10 - Kiyotaka Ichiyama, Masahiro Ishida, Kenichi Nagatani, Toshifumi Watanabe:
A functional test of 2-GHz/4-GHz RF digital communication device using digital tester. 1-10 - X. Cai, Peter Wohl:
A distributed-multicore hybrid ATPG system. 1-7 - Matt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh:
Adaptive testing - Cost reduction through test pattern sampling. 1-8 - Pradip Bose:
Keynote address thursday: Efficient resilience in future systems: Design and modeling challenges. 10 - Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim:
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. 1-10 - David C. Keezer, Carl Edward Gray, Te-Hui Chen, Ashraf Majid:
Practical methods for extending ATE to 40 and 50Gbps. 1-10 - Daisuke Watanabe, Shin Masuda, Hideo Hara, Tsuyoshi Ataka, Atsushi Seki, Atsushi Ono, Toshiyuki Okayasu:
30-Gb/s optical and electrical test solution for high-volume testing. 1-10 - Chun-Kai Hsu, Fan Lin, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, John M. Carulli, Kenneth M. Butler:
Test data analytics - Exploring spatial and test-item correlations in production test data. 1-10 - Hideo Okawara:
Advanced method to refine waveform smeared by jitter in waveform sampler measurement. 1-9 - Praveen Venkataramani, Vishwani D. Agrawal:
ATE test time reduction using asynchronous clock period. 1-10 - Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Fault modeling and diagnosis for nanometric analog circuits. 1-10 - Yang Xue, Osei Poku, Xin Li, Ronald D. Blanton:
PADRE: Physically-Aware Diagnostic Resolution Enhancement. 1-10 - Naoya Azuma, T. Makita, S. Ueyama, Makoto Nagata, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Satoshi Tanaka, Masahiro Yamaguchi:
In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers. 1-9 - Degang Chen, Zhongjun Yu, Krunal Maniar, Mojtaba Nowrozi:
Test time reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitations. 1-9 - Ke Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris:
Process monitoring through wafer-level spatial variation decomposition. 1-10 - Yi Cai, Liming Fang, Ivan Chan, Max Olsen, Kevin Richter:
12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit. 1-8 - Mukesh Agrawal, Krishnendu Chakrabarty:
A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs. 1-10 - Michael B. Cohn, Kaosio Saechao, Michael Whitlock, Daniel Brenman, Wallace T. Tang, Robert M. Proie:
RF MEMS switches for Wide I/O data bus applications. 1-8 - Ke Huang, John M. Carulli, Yiorgos Makris:
Counterfeit electronics: A rising threat in the semiconductor manufacturing industry. 1-4 - Janusz Rajski, Jerzy Tyszer:
Fault diagnosis of TSV-based interconnects in 3-D stacked designs. 1-9 - Mahesh Prabhu, Jacob A. Abraham:
Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults. 1-7 - Afsaneh Nassery, Jae Woong Jeong, Sule Ozev:
Zero-overhead self test and calibration of RF transceivers. 1-9 - John D. Barton:
Keynote address wednesday: Compute continuum and the nonlinear validation challenge. 9 - Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker:
Early-life-failure detection using SAT-based ATPG. 1-10 - Stefano Di Carlo, Giulio Gambardella, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
Fault mitigation strategies for CUDA GPUs. 1-8 - Ming Lu:
An enhanced procedure for calculating dynamic properties of high-performance DAC on ATE. 1-10
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