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ORCIDSuraj Sindia
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2010 – 2019
- 2015
[j5]Suraj Sindia, Vishwani D. Agrawal:
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J. Electron. Test. 31(5-6): 479-489 (2015)- [c14]Suraj Sindia:
Innovative practices session 2C: New technologies, new challenges - 2. VTS 2015: 1 - 2014
- [j4]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A Test Time Theorem and its Applications. J. Electron. Test. 30(2): 229-236 (2014) - [c13]Suraj Sindia, Vishwani D. Agrawal:
Specification test minimization for given defect level. LATW 2014: 1-6 - 2013
- [j3]Suraj Sindia, Vishwani D. Agrawal:
Neural Network Guided Spatial Fault Resilience in Array Processors. J. Electron. Test. 29(4): 473-483 (2013) - [c12]Suraj Sindia, Vishwani D. Agrawal:
High sensitivity test signatures for unconventional analog circuit test paradigms. ITC 2013: 1-10 - [c11]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A test time theorem and its applications. LATW 2013: 1-5 - [c10]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
Finding best voltage and frequency to shorten power-constrained test time. VTS 2013: 1-6 - 2012
- [j2]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. 28(4): 541-549 (2012) - [j1]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electron. Test. 28(5): 757-771 (2012) - [c9]Suraj Sindia, Vishwani D. Agrawal:
Tailoring Tests for Functional Binning of Integrated Circuits. Asian Test Symposium 2012: 95-100 - [c8]Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh:
Impact of process variations on computers used for image processing. ISCAS 2012: 1444-1447 - [c7]Suraj Sindia, Vishwani D. Agrawal:
Towards spatial fault resilience in array processors. VTS 2012: 288-293 - 2011
- [c6]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium 2011: 371-376 - [c5]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Testing linear and non-linear analog circuits using moment generating functions. LATW 2011: 1-6 - [c4]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS 2011: 64-69 - 2010
- [c3]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design 2010: 288-293
2000 – 2009
- 2009
- [c2]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium 2009: 63-68 - [c1]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI 2009: 69-74
Coauthor Index
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