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ORCIDTapan J. Chakraborty
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2010 – 2019
- 2013
[c20]Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor:
Functional Fmax test-time reduction using novel DFTs for circuit initialization. ICCD 2013: 1-6- 2010
- [j7]Michele Portolan
, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook:
A Common Language Framework for Next-Generation Embedded Testing. IEEE Des. Test Comput. 27(5): 36-49 (2010)
2000 – 2009
- 2008
- [c19]Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook:
A New Language Approach for IJTAG. ITC 2008: 1-10 - [c18]Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty:
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. VLSI Design 2008: 39-44 - 2007
- [c17]Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty:
A TMR Scheme for SEU Mitigation in Scan Flip-Flops. ISQED 2007: 905-910 - [c16]Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren:
A practical approach to comprehensive system test & debug using boundary scan based test architecture. ITC 2007: 1-10 - [c15]Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook:
FPGA Prototyping of a Scan Based System-On-Chip Design. ReCoSoC 2007: 121-126 - 2005
- [c14]Tapan J. Chakraborty:
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. Asian Test Symposium 2005: 464-465 - 2002
- [c13]Tapan J. Chakraborty, Chen-Huan Chiang:
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. ITC 2002: 923-929 - 2000
- [j6]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 223-228 (2000) - [j5]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 736-741 (2000)
1990 – 1999
- 1999
- [j4]Nilanjan Mukherjee, Tapan J. Chakraborty, Ramesh Karri:
Built in self test: a complete test solution for telecommunication systems. IEEE Commun. Mag. 37(6): 72-78 (1999) - 1998
- [c12]Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik:
A BIST scheme for the detection of path-delay faults. ITC 1998: 422-431 - 1997
- [j3]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
On variable clock methods for path delay testing of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1237-1249 (1997) - [c11]Tapan J. Chakraborty, Vishwani D. Agrawal:
Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC 1997: 998-1003 - 1996
- [c10]Tapan J. Chakraborty, Vishwani D. Agrawal:
Design for high-speed testability of stuck-at faults. VLSI Design 1996: 53-56 - 1995
- [c9]Vishwani D. Agrawal, Tapan J. Chakraborty:
High-Performance Circuit Testing with Slow-Speed Testers. ITC 1995: 302-310 - [c8]Tapan J. Chakraborty, Vishwani D. Agrawal:
Robust testing for stuck-at faults. VLSI Design 1995: 42-46 - [c7]Tapan J. Chakraborty, Vishwani D. Agrawal:
Simulation of at-speed tests for stuck-at faults. VTS 1995: 216-220 - 1994
- [c6]Tapan J. Chakraborty, Vishwani D. Agrawal:
Delay independent initialization of sequential circuits. Great Lakes Symposium on VLSI 1994: 228-230 - 1993
- [c5]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Design for Testability for Path Delay faults in Sequential Circuits. DAC 1993: 453-457 - [c4]Vishwani D. Agrawal, Tapan J. Chakraborty:
Partial scan testing with single clock control. VTS 1993: 313-315 - 1992
- [c3]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC 1992: 165-172 - 1991
- [j2]Sumit Ghosh, Tapan J. Chakraborty:
On behavior fault modeling for digital designs. J. Electron. Test. 2(2): 135-151 (1991) - [c2]Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin:
Enhanced Controllability for IDDQ Test Sets Using Partial Scan. DAC 1991: 278-281
1980 – 1989
- 1989
- [j1]Wu-Tung Cheng, Tapan J. Chakraborty:
Gentest: An Automatic Test-Generation System for Sequential Circuits. Computer 22(4): 43-49 (1989) - 1988
- [c1]Tapan J. Chakraborty, Sumit Ghosh:
On Behavior Fault Modeling for Combinational Digital Designs. ITC 1988: 593-600
Coauthor Index
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