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ORCIDTakeomi Tamesada
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2000 – 2009
- 2006
[c23]Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura:
Current Testable Design of Resistor String DACs. DELTA 2006: 197-200- 2005
- [c22]Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Electric field for detecting open leads in CMOS logic circuits by supply current testing. ISCAS (3) 2005: 2995-2998 - 2004
- [j7]Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada:
Test Sequence Generation for Test Time Reduction of IDDQ Testing. IEICE Trans. Inf. Syst. 87-D(3): 537-543 (2004) - [j6]Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits. IEICE Trans. Inf. Syst. 87-D(3): 571-579 (2004) - [j5]Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
A test circuit for pin shorts generating oscillation in CMOS logic circuits. Syst. Comput. Jpn. 35(13): 10-20 (2004) - [c21]Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada:
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. Asian Test Symposium 2004: 112-117 - [c20]Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS Open Fault Detection by Appearance Time of Switching Supply Current. DELTA 2004: 183-188 - [c19]Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Practical Fault Coverage of Supply Current Tests for Bipolar ICs. DELTA 2004: 189-194 - [c18]Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. DELTA 2004: 306-311 - 2003
- [c17]Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita:
A BIST Circuit for IDDQ Tests. Asian Test Symposium 2003: 390-395 - 2002
- [c16]Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada:
Test Time Reduction for I DDQ Testing by Arranging Test Vectors. Asian Test Symposium 2002: 423-428 - [c15]Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada:
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. DELTA 2002: 387-391 - [c14]Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. DELTA 2002: 459-461 - 2001
- [c13]Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada:
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. Asian Test Symposium 2001: 23- - [c12]Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. Asian Test Symposium 2001: 117-122 - [c11]Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS open defect detection by supply current test. DATE 2001: 509 - [c10]Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada:
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. DFT 2001: 287- - 2000
- [c9]Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda:
High speed IDDQ test and its testability for process variation. Asian Test Symposium 2000: 344-349 - [c8]Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda:
Testability Analysis of IDDQ Testing with Large Threshold Value. DFT 2000: 367-375
1990 – 1999
- 1999
- [c7]Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Identification of Feedback Bridging Faults with Oscillation. Asian Test Symposium 1999: 25- - 1998
- [c6]Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita:
A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium 1998: 327- - 1997
- [c5]Masaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada:
Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates. Asian Test Symposium 1997: 372-377 - 1996
- [c4]Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada:
Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. Asian Test Symposium 1996: 171-176 - 1994
- [c3]Masaki Hashizume, Takeomi Tamesada, Akio Sakamoto:
A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines. ISCAS 1994: 193-196 - 1990
- [c2]Masaki Hashizume, Takeomi Tamesada, Koji Nii:
A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. ICCD 1990: 24-28
1980 – 1989
- 1989
- [j4]Takeomi Tamesada:
High-speed multioperand addition and subtraction using a p-ary representation with necessary and minimum redundancy. Syst. Comput. Jpn. 20(4): 59-70 (1989) - [j3]Masaki Hashizume, Hirosuke Yamamoto
, Takeomi Tamesada, Toshiaki Hanibuti:
Evaluation of a retrieval system using content addressable memory. Syst. Comput. Jpn. 20(7): 1-9 (1989) - 1988
- [j2]Takeomi Tamesada:
High-speed addition and subtraction using a minimum redundant p-ary representation. Syst. Comput. Jpn. 19(11): 33-39 (1988) - [c1]Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami:
Fault Detection of Combinational Circuits Based on Supply Current. ITC 1988: 374-380 - 1980
- [j1]Takeomi Tamesada:
Sequential Machines Having Quasi-Stable States. IEEE Trans. Computers 29(5): 405-408 (1980)
Coauthor Index
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