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ORCIDErnst G. Ulrich
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1990 – 1999
- 1994
[b1]Ernst G. Ulrich, Vishwani D. Agrawal, Jack H. Arabian:
Concurrent and comparative discrete event simulation. Kluwer 1994, ISBN 978-0-7923-9411-2, pp. I-XIII, 1-186- 1993
- [j7]Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich:
Clock suppression techniques for synchronous circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1547-1556 (1993) - 1992
- [j6]Ernst G. Ulrich, Karen Lentz, Jack H. Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro:
The Comparative and Concurrent Simulation of discrete-event experiments. J. Electron. Test. 3(2): 107-118 (1992) - 1991
- [c15]Ernst G. Ulrich, Karen Panetta Lentz, Stephen R. Demba, Rahul Razdan:
Concurrent MIN-MAX simulation. EURO-DAC 1991: 554-557 - 1990
- [j5]Stephen R. Demba, Ernst G. Ulrich, Karen Panetta Lentz, David Giramma:
Experiences with concurrent fault simulation of diagnostic programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 621-628 (1990) - [c14]Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich:
Exploitation of Periodicity in Logic Simulation of Synchronous Circuits. ICCAD 1990: 62-65
1980 – 1989
- 1988
- [c13]Deborah Machlin, David Gross, Sudhir Kadkade, Ernst G. Ulrich:
Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal Mechanism. ITC 1988: 574-581 - [c12]Stephen R. Demba, Ernst G. Ulrich, Karen Panetta, David Giramma:
Experiences with Concurrent Fault Simulation of Diagnostic Programs. ITC 1988: 877-883 - 1987
- [j4]Silvano Gai, Fabio Somenzi, Ernst G. Ulrich:
Advances in Concurrent Multilevel Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1006-1012 (1987) - 1985
- [c11]Ernst G. Ulrich:
Concurrent Simulation at the Switch, Gate, and Register Levels. ITC 1985: 703-709 - 1983
- [c10]Ernst G. Ulrich:
A design verification methodology based on concurrent simulation and clock suppression. DAC 1983: 709-712 - 1982
- [c9]Ernst G. Ulrich, Dennis Hebert:
Speed and accuracy in digital network simulation based on structural modeling. DAC 1982: 587-593 - 1980
- [c8]Ernst G. Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven:
High-speed concurrent fault simulation with vectors and scalars. DAC 1980: 374-380 - [c7]Ernst G. Ulrich:
Table lookup techniques for fast and flexible digital logic simulation. DAC 1980: 560-563
1970 – 1979
- 1978
- [j3]Ernst G. Ulrich:
Event Manipulation for Discrete Simulations Requiring Large Numbers of Events. Commun. ACM 21(9): 777-785 (1978) - 1975
- [c6]Donald M. Schuler, Ernst G. Ulrich, Thomas E. Baker, Susan P. Bryant:
Random test generation using concurrent logic simulation. DAC 1975: 261-267 - 1974
- [j2]Ernst G. Ulrich, Thomas E. Baker:
Concurrent simulation of nearly identical digital networks. Computer 7(4): 39-44 (1974) - 1973
- [c5]Ernst G. Ulrich, Thomas E. Baker:
The concurrent simulation of nearly identical digital networks. DAC 1973: 145-150 - 1972
- [c4]Donald M. Schuler, Ernst G. Ulrich:
Clustering and linear placement. DAC 1972: 50-56 - [c3]Ernst G. Ulrich, Thomas E. Baker, L. R. Williams:
Fault-test analysis techniques based on logic simulation. DAC 1972: 111-115
1960 – 1969
- 1969
- [j1]Ernst G. Ulrich:
Exclusive simulation of activity in digital networks. Commun. ACM 12(2): 102-110 (1969) - 1968
- [c2]Ernst G. Ulrich:
Serial/parallel event scheduling for the simulation of large systems. ACM National Conference 1968: 279-287 - 1965
- [c1]Ernst G. Ulrich:
Programming languages for non-numeric processing - 2: Time sequenced logical simulation based on circuit delay and selective tracing of active network paths. ACM National Conference 1965: 437-448
Coauthor Index
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