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ORCIDNaveena Nagi
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1990 – 1999
- 1999
[c13]Stephen K. Sunter, Naveena Nagi:
Test Metrics for Analog Parametric Faults. VTS 1999: 226-235- 1998
- [j4]Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham:
Signature analysis for analog and mixed-signal circuit test response compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 540-546 (1998) - [c12]Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi:
Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. VTS 1998: 145-151 - 1997
- [c11]Stephen K. Sunter, Naveena Nagi:
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. ITC 1997: 389-395 - [c10]Abhijit Chatterjee, Naveena Nagi:
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. VLSI Design 1997: 388-392 - [c9]Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi:
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. VTS 1997: 261-266 - 1996
- [j3]Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi:
DC Built-In Self-Test for Linear Analog Circuits. IEEE Des. Test Comput. 13(2): 26-33 (1996) - [j2]Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A unified approach for fault simulation of linear mixed-signal circuits. J. Electron. Test. 9(1-2): 29-41 (1996) - [c8]Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi:
Low-cost DC built-in self-test of linear analog circuits using checksums. VLSI Design 1996: 230-233 - 1995
- [c7]Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham:
Efficient multisine testing of analog circuits. VLSI Design 1995: 234-238 - 1994
- [c6]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A Signature Analyzer for Analog and Mixed-signal Circuits. ICCD 1994: 284-287 - 1993
- [j1]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
Fault simulation of linear analog circuits. J. Electron. Test. 4(4): 345-360 (1993) - [c5]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
DRAFTS: Discretized Analog Circuit Fault Simulator. DAC 1993: 509-514 - [c4]Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham:
Fault-based automatic test generator for linear analog circuits. ICCAD 1993: 88-91 - [c3]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
MIXER: Mixed-Signal Fault Simulator. ICCD 1993: 568-571 - 1992
- [c2]Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu:
Delay fault testing of iterative arithmetic arrays. VTS 1992: 25-30 - [c1]Naveena Nagi, Jacob A. Abraham:
Hierarchical fault modeling for analog and mixed-signal circuits. VTS 1992: 96-101
Coauthor Index
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