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ORCIDGary S. Ditlow
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2010 – 2019
- 2011
[c7]Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC 2011: 256-258
2000 – 2009
- 2007
- [c6]Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
:
Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262
1990 – 1999
- 1999
- [c5]Gary S. Ditlow, Anshul Gupta, Richard L. Moore, David Moran, Ralph Williams, Tom Wilkins:
Parallel Analysis of IC Power Distribution Networks. PP 1999 - [c4]David Moran, Gary S. Ditlow, Daria Dooling, Ralph Williams, Tom Wilkins:
Integrated Manufacturing and Development (IMaD). SC 1999: 9 - 1992
- [c3]David A. Zein, Oliver P. Engel, Gary S. Ditlow:
HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. DAC 1992: 432-437 - [c2]David A. Zein, Oliver P. Engel, Gary S. Ditlow:
Algorithms for the design verification of bipolar array chips. VTS 1992: 327-332 - [c1]David A. Zein, Oliver P. Engel, Gary S. Ditlow:
HLSIM-a new hierarchical logic simulator in APL. VTS 1992: 333-338
1980 – 1989
- 1984
- [j1]Jacob Savir, Gary S. Ditlow, Paul H. Bardell:
Random Pattern Testability. IEEE Trans. Computers 33(1): 79-90 (1984)
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