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ORCID18th LATS 2017: Bogotá, Colombia
- 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017. IEEE 2017, ISBN 978-1-5386-0415-1
- Alberto Bosio, Arnaud Virazel
, Patrick Girard, Mario Barbareschi:
Approximate computing: Design & test for integrated circuits. 1 - Nandeesha Veeranna, Benjamin Carrión Schäfer:
Efficient behavioral intellectual properties source code obfuscation for high-level synthesis. 1-6 - Vaibhav Venugopal Rao, Ioannis Savidis:
Protecting analog circuits with parameter biasing obfuscation. 1-6 - André Lucas Chinazzo, Paulo César Comassetto de Aguirre, Tiago R. Balen:
Low cost automatic test vector generation for structural analog testing. 1-4 - Satoshi Ohtake, Daichi Shimazu:
An approach to LFSR-based X-masking for built-in self-test. 1-4 - Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt:
Fault injection methodology for single event effects on clock-gated ASICs. 1-4 - Gabriel S. Porto, Paulo F. Butzen, Denis Teixeira Franco:
Exploring BDDs to reduce test pattern set. 1-4 - Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez:
An effective strategy for selective hardening of software. 1-6 - Alejandro David Velasco, Bartolomeo Montrucchio, Maurizio Rebaudengo:
TMR technique for mutex kernel data structures. 1-6 - Andrea Floridia, R. Margelli, Ernesto Sánchez:
On the development of a high-level fault simulator for the analysis of performance faults on speculative modules. 1-6 - Fabio Benevenuti, Fernanda Lima Kastensmidt:
Evaluation of fault attack detection on SRAM-based FPGAs. 1-6 - M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco:
Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. 1-4 - Vinicius Martins, Jiang Chau Wang, Jerson Paulo Guex:
Mixed signal verification to avoid integration mismatch in complex SoCs. 1-6 - Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez:
Analysis of the implications of stacked devices in nano-scale technologies for analog applications. 1-4 - Carlos J. González, Cristiano P. Chenet, Matheus Budelon, Rafael Galhardo Vaz, Odair Lelis Goncalez, Tiago R. Balen:
Evaluation of a mixed-signal design diversity system under radiation effects. 1-6 - Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker:
Evaluating the effectiveness of D-chains in SAT-based ATPG. 1-6 - Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh:
Testing multiple stuck-at faults of ROBDD based combinational circuit design. 1-6 - Oscar Acevedo Patino, Juan Carlos Martínez Santos:
Physical-aware pattern selection for stuck-at faults. 1-5 - Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
Analysis of short defects in FinFET based logic cells. 1-6 - Felix Mühlbauer, Lukas Schröder, Patryk Skoncej, Mario Schölzel:
Handling manufacturing and aging faults with software-based techniques in tiny embedded systems. 1-6 - Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
Identifying high variability speed-limiting paths under aging. 1-6 - Oscar Acevedo, Dimitri Kagaris:
LFSR characteristic polynomial and phase shifter computation for two-dimensional test set generation. 1-6 - Gaiping An, Riccardo Cantoro, Ernesto Sánchez, Matteo Sonza Reorda:
On the detection of board delay faults through the execution of functional programs. 1-6 - Enea Bagalini, Jacopo Sini, Matteo Sonza Reorda, Massimo Violante, H. Klimesch, Peter Sarson:
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard. 1-6 - Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Post-silicon observability enhancement with topology based trace signal selection. 1-6 - Felipe G. H. Leite, Roberto B. B. Santos, Nilberto H. Medina, Vitor A. P. Aguiar, Renato C. Giacomini, Nemitala Added, Fernando Aguirre, Eduardo L. A. Macchione, Fabian Vargas, Marcilei Aparecida Guazzelli da Silveira:
Ionizing radiation effects on a COTS low-cost RISC microcontroller. 1-4 - Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco:
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. 1-4 - Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt:
Evaluating the behavior of successive approximation algorithms under soft errors. 1-6 - Matheus Berger Oliveira, Joao de Moraes, Sérgio Luis Cechin, Taisy Silva Weber, Joao Netto:
Practical experience designing and debugging an FPGA for a real-time ethernet industrial bus. 1-6 - Paolo Bernardi, Riccardo Cantoro, L. Gianotto, Marco Restifo, Ernesto Sánchez, Federico Venini, Davide Appello:
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller. 1-6 - Ronaldo Milfont, Paulo Cortez, Alan Cadore Pinheiro, Joao Marcelo Ferreira, Jarbas Silveira, Rafael Mota, César A. M. Marcon:
Analysis of routing algorithms generation for irregular NoC topologies. 1-5 - Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips. 1-4 - Israel C. Lopes, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin:
SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA. 1-6 - Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre:
Contrast of a HDL model and COTS version of a microprocessor for soft-error testing. 1-6 - Paulo Ricardo Cechelero Villa, Roger C. Goerl, Fabian Vargas, Leticia B. Poehls, Nilberto H. Medina, Nemitala Added, Vitor A. P. de Aguiar, Eduardo L. A. Macchione, Fernando Aguirre, Marcilei Aparecida Guazzelli da Silveira, Eduardo Augusto Bezerra:
Analysis of single-event upsets in a Microsemi ProAsic3E FPGA. 1-4
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