default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID4th LASCAS 2013: Cusco, Peru
- 4th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2013, Cusco, Peru, February 27 - March 1, 2013. IEEE 2013, ISBN 978-1-4673-4897-3
- Luis Eduardo Toledo, Pablo A. Petrashin, Walter J. Lancioni, Fortunato Carlos Dualibe, Luis Rafael Canali:
A low voltage CMOS voltage reference based on partial compensation of MOSFET threshold voltage and mobility using current subtraction. 1-4 - Enrique Alvarez, Diego Avila, Hernan Campillo, Angel Abusleme
:
Fully-differential offset-cancelling circuit with configurable output common-mode voltage. 1-3 - Dionisio de Carvalho, João Navarro:
A power optimized decimator for sigma-delta data converters. 1-4 - Lancelot Garcia-Leyva, Antonio Calomarde, Francesc Moll, Antonio Rubio:
Novel redundant logic design for noisy low voltage scenarios. 1-4 - Marcio Bender Machado, Márcio Cherem Schneider, Carlos Galup-Montoro:
Analysis and design of ultra-low-voltage inductive ring oscillators for energy-harvesting applications. 1-4 - Óscar Robles, Fernando Baruqui:
Very-low-tranconductance CMOS amplifier using multi-tanh bulk-driven input stage with gate-controlled assymetry for Gm-C applications. 1-4 - Amaro A. de Lima, Thiago de M. Prego, Sergio L. Netto, Eduardo A. B. da Silva, Ricardo H. R. Gutiérrez, Ulisses A. Monteiro, Antonio C. R. Troyman, Francisco J. da C. Silveira, Luiz A. P. Vaz:
On fault classification in rotating machines using fourier domain features and neural networks. 1-4 - Miok Kim, Nam Ling, John D. Ralston, Li Song:
A mesh-based method for wavelet video coding using edge-detection in low frequency subband. 1-4 - Yuki Tsukui, Kenichi Okada, Akira Matsuzawa:
A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakage. 1-4 - Nicolas Laflamme-Mayer, Mohamad Sawan, Yves Blaquière:
A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. 1-4 - Paulo Renato de Souza Silva Sandres, Nadia Nedjah, Luiza de Macedo Mourelle:
Massively parallel scalable reconfigurable hardware for fuzzy controllers. 1-4 - Gianluca Forte, John M. Espinosa-Duran, Jaime Velasco-Medina:
Systolic architectures to evaluate polynomials of degree n using the Horner's rule. 1-4 - Vladimir Afonso, Henrique Maich, Luciano Agostini, Denis Franco:
Low cost and high throughput FME interpolation for the HEVC emerging video coding standard. 1-4 - Joel Gak, Matías R. Miguez, Alfredo Arnaud:
A programmable charge pump voltage converter for implantable medical devices in a HV technology. 1-4 - Angelo Goncalves da Luz, Eduardo A. C. da Costa, Sidinei Ghissoni:
Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms. 1-4 - Rogério M. Calazan, Nadia Nedjah, Luiza de Macedo Mourelle:
Parallel GPU-based implementation of high dimension Particle Swarm Optimizations. 1-4 - Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans:
Design of NCL gates with the ASCEnD flow. 1-4 - Raul Aragonés, Joan Oliver, Carles Ferrer:
A system clock precision frequency to code converter for low power supply dependence ROIC. 1-4 - Emmanuel Torres-Rios, Svetlana Carsof Sejas Garcia, Luiz Carlos Moreira, Reydezel Torres-Torres, Wilhelmus A. M. Van Noije:
Analysis of the effects of coupling through substrate and the calculus of the Q factor. 1-4 - Takashi Kambe, Kohsei Takehara, Shuji Tsukiyama:
Application-specific arithmetic circuit design for a particle tracking application. 1-4 - Carlos Hernández-Mejía, Arturo Sarmiento-Reyes, Hector Vazquez-Leal:
A family of memristive transfer functions of negative feedback nullor-based amplifiers. 1-4 - Antônio Carlos M. de Queiroz:
Electrostatic generators for vibrational energy harvesting. 1-4 - Ignatius Bezzam, Shoba Krishnan, Tezaswi Raja, Chakravarthy Mathiazhagan:
Low power low voltage wide frequency resonant clock and data circuits for power reductions. 1-4 - Gustavo Seibel, Fábio P. Itturriet, Eduardo Costa, Sérgio Almeida:
Fixed-point adaptive filter architecture for the harmonics power line interference cancelling. 1-4 - M. T. Kousoulis, G. E. Antoniou:
Realization of 4D lattice structured digital filters. 1-4 - Raymundo Cassani, Juan Carlos Sanchez, Raul Martinez:
Implementation and evaluation of an adaptive method for reduce the respiration influence on Heart Rate Variability. 1-4 - Edward Steven Oliveros Ortiz, Faruk Fonthal Rico, Gilberto M. Bolaños P.:
DC and AC electrical characterization temperature dependence of Ag/Porous Silicon/p-Si/Al. 1-4 - Odilon O. Dutra, Tales C. Pimenta:
Low power low noise bio-amplifier with adjustable gain for digital bio-signals acquisition systems. 1-4 - Dalton M. Colombo, Gilson I. Wirth, Sergio Bampi, P. Srinivasan:
Voltage reference design using 1 V power supply in 0.13 µm CMOS technology. 1-4 - F. J. De Marco, José Antonio Apolinário, Paulo Cesar Pellanda, N. Martins:
Efficient online estimation of electromechanical modes in large power systems. 1-4 - Reza Abdullah, Edgar Sánchez-Sinencio:
A biopotential amplifier with improved common mode gain. 1-4 - Fernando Aparicio Urbano-Molano, Vladimir Trujillo-Olaya, Jaime Velasco-Medina:
Design of an elliptic curve cryptoprocessor using optimal normal basis over GF(2233). 1-4 - Gustavo Sanchez, Marcelo Schiavon Porto, Luciano Agostini:
A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applications. 1-4 - Nobuyuki Araki, Takashi Kambe:
A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuits. 1-4 - Sofiane Aloui, Bernardo Leite, Nejdat Demirel, Robert Plana, Didier Belot, Eric Kerherve:
Optimization of 65nm CMOS passive devices to design a 16 dBm-Psat 60 GHz power amplifier. 1-4 - Carlos Sánchez-López, Rocio Ochoa-Montiel, A. Ruiz-Pastor, B. M. Gonzalez-Contreras:
Symbolic nodal analysis of fully-differential analog circuits. 1-4 - Leonardo Bandeira Soares, Kleber Stangherlin, Jorge de Mello, Sergio Bampi:
61 pJ/sample near-threshold notch filter with pole-radius variation. 1-4 - Zdenek Kolka, Jaroslav Kalous, Viera Biolková, Dalibor Biolek:
Program for symbolic analysis of mechatronic systems. 1-4 - Ryan Selby, Kern Tucker, William Wilson, Tom Chen:
A 0.18µm CMOS switched-capacitor amplifier using current-starving inverter based op-amp for low-power biosensor applications. 1-4 - Dieison Silveira, Marcelo Schiavon Porto, Luciano Agostini:
A real time high definition architecture for the Variable-Length Reference Frame Decoder. 1-4 - Victor Ferreira Pereira, Edward David Moreno, Wanderson Roger Azevedo Dias, Dellano Oliveira D. dos Santos:
Specific processor in FPGA for BLAKE algorithm. 1-5 - Milton E. Conde, Sérgio Cruz, Daniel M. Muñoz, Carlos H. Llanos, Eugênio L. F. Fortaleza:
An efficient data fusion architecture for infrared and ultrasonic sensors, using FPGA. 1-4 - Julio Viola, Flavio Quizhpi, Gustavo Parra:
Vector analysis of a four-phase induction machine. 1-4 - Oscar Ricardo Acosta del Campo, César Cruz-Hernández, Adrian Arellano-Delgado, Rosa Martha López-Gutiérrez:
Communication in star coupled network with fractional hyperchaotic nodes. 1-4 - Shuji Tsukiyama, Masahiro Fukui, Takashi Kambe:
A new delay distribution model to take long-term degradation into account. 1-4 - Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Design of a multiband full-rate ultra-wideband receiver in FPGA. 1-4 - Jesús Efraín Gaxiola Sosa, Kamran Entesari:
A wireless medical system prototype for implantable applications. 1-4 - Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto:
Design of a massively parallel computing architecture for dense matrix multiplication. 1-4 - Thiago P. R. Goes, Robson Nunes de Lima, Luciana Martinez, Fernando Rangel de Sousa:
A design technique for distributed dual-band bandpass filters. 1-4 - Jonas Gomes Filho, Marius Strum, Wang Jiang Chau:
A strategy for mapping reconfigurable cores in NoCs. 1-4 - Sérgio Cruz, Daniel M. Muñoz, Milton E. Conde, Carlos H. Llanos, Geovany A. Borges:
FPGA implementation of a sequential Extended Kalman Filter algorithm applied to mobile robotics localization problem. 1-4 - Dayanne K. F. R. Escale, Karla D. N. Ramos, Cláudia M. F. A. Ribeiro:
Formalism and reuse in NoC design. 1-4 - Pavel Zahradnik, Boris Simák, Miroslav Vlcek:
Narrow-band FIR filter sets. 1-4 - Juan Gerardo Ávalos Ochoa, Juan C. Sánchez, José Velázquez López:
Error coded affine projection algorithm. 1-4 - Francisco Veirano, Pablo Perez-Nicoli, Sebastian Besio, Pablo Castro-Lisboa, Fernando Silveira:
Ultra low power pulse generator based on a ring oscillator with direct path current avoidance. 1-4 - Andrius Petrovas, Elena Tamaseviciute, Gytis Mykolaitis, Arünas Tamasevicius, Ruedi Stoop:
Analog circuits for modeling and controlling synchrony in arrays of coupled oscillators. 1-4 - Jorge E. Guerrero-Ramirez, Jaime Velasco-Medina, Julio C. Arce-Clavijo:
Hardware design of an eigensolver based on the QR method. 1-4 - Cristina Meinhardt, Ricardo Reis:
FinFET basic cells evaluation for regular layouts. 1-4 - Luis Antonio Carrillo-Martínez, Guillermo Espinosa Flores-Verdad:
7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier. 1-4 - Renato Coral Sampaio, Pedro de Azevedo Berger, Ricardo P. Jacobi:
High-level design and synthesis of a MPEG-4 AAC IMDCT module. 1-4 - Luiz Carlos Moreira, Jose Fontebasso Neto, Wilhelmus A. M. Van Noije, Emmanuel Torres-Rios:
Inductorless very small 2nd derivative Gaussian IRUWB transmitter module using n/p-latches as PDs in CMOS technology. 1-4 - Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla:
Efficient parallel scheduler for circuit simulation exploiting binary link formulations. 1-4 - Hector Ivan Gomez Ortiz:
Enhanced DC gain amplifier using no miller capacitor feedforward compensation. 1-4 - Luneque Silva Junior, Nadia Nedjah, Luiza de Macedo Mourelle:
ACO approach in static routing for network-on-chips with 3D mesh topology. 1-4 - Greicy Marques-Costa, Wassim Mansour, Fabrice Pancher, Raoul Velazco, Alain Bui, Devan Sohier:
Optimization of a self-converging algorithm at assembly level to improve SEU fault-tolerance. 1-4 - Duarte Lopes de Oliveira, Diego Bompean, Tiago S. Curtinhas, Lester de Abreu Faria:
Design of locally-clocked asynchronous finite state machines using synchronous CAD tools. 1-4 - Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano:
Design of synchronous pipeline digital systems operating in double-edge of the clock. 1-4 - Paulo César Comassetto de Aguirre, Vinicius Camargo, Hamilton Klimach, Altamiro Amadeu Susin, Cesar Prior:
Behavioral modeling of continuous-time ΣΔ modulators in matlab/simulink. 1-4 - William Wilson, Tom Chen, Ryan Selby:
A current-starved inverter-based differential amplifier design for ultra-low power applications. 1-4 - Jonghyun Cho, Joungho Kim:
Signal integrity design of TSV and interposer in 3D-IC. 1-4 - Wolfgang Schreiber-Prillwitz, Reinhart Job:
Designing MEMS pressure sensors with integrated circuitry on silicon for miscellaneous applications. 1-4 - Emrah Armagan, Hakan Kuntman:
Configurable frequency agile filter application of balanced differential pair based CCCII circuit in 28nm process. 1-4 - Angel J. Soto, Esteban O. Lindstrom, Alejandro R. Oliva, Pablo Sergio Mandolesi, Fortunato Carlos Dualibe:
Fully integrated single-inductor multiple-output (SIMO) DC-DC converter in CMOS 65 nm technology. 1-4 - Ricardo Doldán, Antonio J. Ginés, Adoración Rueda:
Inductor characterization in RF LC-VCOs. 1-4 - Jorge González, Gustavo A. Patiño-Álvarez, Marius Strum, Wang Jiang Chau:
Long range dependence in intrachip transaction level traffic. 1-4 - Santiago Martin Sondón, Pablo Sergio Mandolesi, Favio R. Masson, Pedro Julián, Felix Palumbo:
A dual core low power microcontroller with openMSP430 architecture for high reliability lockstep applications using a 180 nm high voltage technology node. 1-4 - Firat Kaçar, Ayten Kuntman, Hakan Kuntman:
Mixed-mode biquad filter employing single active element. 1-4 - Edgar J. Garcia Neto Segundo, Nadia Nedjah, Luiza de Macedo Mourelle:
A scalable parallel reconfigurable hardware architecture for DNA matching. 1-4 - Hugo Daniel Hernández, Sergio Takeo Kofuji, Wilhelmus A. M. Van Noije:
Fully integrated boost converter for thermoelectric energy harvesting. 1-3 - Cagri Gurleyuk, Burcin Pak, Devrim Yilmaz Aksin:
A frequency to voltage converter based on an accurate pulse width modulator for frequency locked loops. 1-4 - Edson Sorato, Renan Netto, Pedro Michel, José Luís Güntzel, Adalbery R. Castro, Aldebaro Klautau:
VLSI architectures for Digital Modulation Classification using Support Vector Machines. 1-4 - Manuel J. Barragán, Gildas Léger, Diego Vázquez, Adoración Rueda:
Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique. 1-4 - Zdenek Kolka, Michal Kubícek, Viera Biolková, Dalibor Biolek:
Non-stationary statistical simulation of blind-oversampling CDR circuits. 1-4 - Hamilton Klimach, Moacir Fernandes Cortinhas Monteiro, Arthur Liraneto Torres Costa, Sergio Bampi:
A resistorless switched bandgap reference topology. 1-4 - Andres Amaya, Francisco Villota, Guillermo Espinosa:
A robust to PVT fully-differential amplifier in 45nm SOI-CMOS technology. 1-4 - Felipe da Rocha Henriques, Lisandro Lovisolo, Marcelo Gonçalves Rubinstein:
Algorithms for energy efficient reconstruction of a process with a multihop Wireless Sensor Network. 1-4 - Carlos Sánchez-López, Jorge Mendoza-Lopez, Carlos Muñiz-Montero, Luis Abraham Sánchez-Gaspariano, Jesús M. Muñoz-Pacheco:
Accuracy vs simulation speed trade-off enhancements in the generation of chaotic attractors. 1-4 - Pavel Zahradnik, Boris Simák, Miroslav Vlcek:
Closed form design of nearly equiripple low-pass FIR filters. 1-4 - José E. Schutt-Ainé, Patrick Goh:
Phase-locked loop simulations using the latency insertion method. 1-4 - Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Transistor-level optimization of CMOS complex gates. 1-4 - Jonathan Hernandez, Tugrul Zure, Sazzadur Chowdhury:
Capacitance measurements of an SOI based CMUT. 1-4 - Salim Lahmiri, Mounir Boukadoum:
An application of the empirical mode decomposition to brain magnetic resonance images classification. 1-4 - Marcos L. Carneiro, Nathalie Deltimple, Didier Belot, Paulo Henrique Portela de Carvalho, Eric Kerherve:
A 2.535 GHz fully integrated Doherty power amplifier in CMOS 65nm with constant PAE in backoff. 1-4 - Roberto de Moura Estevão Filho, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia:
Codebook improvements for a CMOS imager with focal-plane vector quantization. 1-4 - Carlos Rivera-Escobar, Fransisco Silva-Del-Rosario, Miguel Silva-Martinez, Ivan R. Padilla-Cantoya:
Multiple stage capacitor multiplier using dual-output differential amplifiers. 1-3 - Christina Gimmler-Dumont, Philipp Schläfer, Norbert Wehn:
ASIC implementation of a modified QR decomposition for tree search based MIMO detection. 1-4 - Heiner Alarcon Cubas, Joao Navarro Soares Jr.:
Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodology. 1-4 - Shantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske:
Fast floorplanning with placement constraints. 1-4 - Camilo Sánchez-Ferreira, Jones Yudi Mori, Carlos H. Llanos, Eugênio L. F. Fortaleza:
Development of a stereo vision measurement architecture for an underwater robot. 1-4 - Jorge Luis González Rios, Juan Carlos Cruz, Diego Vázquez, Adoración Rueda:
Analysis of process variations' impact on a 2.4 GHz 90 nm CMOS LNA. 1-4 - José Ernesto Rayas-Sánchez, Zabdiel Brito-Brito, Juan C. Cervantes-González, Carlos A. Lopez:
Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures. 1-4 - Chin-Long Wey, Chung-Hsien Hsu, Tai-Wei Chang:
A voltage-mode boost DC-DC converter with a constant-duty-cycle pulse control. 1-4 - Antonio J. López-Martín, Alfonso Carlosena:
Sensor signal linearization techniques: A comparative analysis. 1-4 - Iman Moazzen, Panajotis Agathoklis:
Analysis of a broadband beamformer based on trapezoidal filters and nested arrays. 1-4 - Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, César Pedraza, Wang Jiang Chau, Marius Strum:
QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs. 1-4 - Wanderson Roger Azevedo Dias, Edward David Moreno:
Code compression using Multi-Level Dictionary. 1-4 - Kern Tucker, Tom Chen:
A low-power, offset-corrected potentiostat for chemical imaging applications. 1-4 - César Torres-Huitzil:
Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption. 1-4 - Mariana Natalia Ibarra-Bonilla, Ponciano Jorge Escamilla-Ambrosio, Juan Manuel Ramírez-Cortés, Carlos Vianchada:
Pedestrian dead reckoning with attitude estimation using a fuzzy logic tuned adaptive kalman filter. 1-4 - Claudia Patricia Renteria-Mejia, Vladimir Trujillo-Olaya, Jaime Velasco-Medina:
8912-bit Montgomery multipliers using radix-8 booth encoding and coded-digit. 1-4 - Marcelo Macchi da Silva, Jose Fontebasso Neto, Luiz Carlos Moreira, Jacobus W. Swart:
A motion detection pixel system using an inductorless UWB transmitter on standard 0.35µm/CMOS technology. 1-4 - David Cordova, Eric E. Fabris, Renato Campana V.:
An efficient CMOS configurable Bias Current Generator with wide dynamic range. 1-4 - Ismael Seidel, Bruno George de Moraes, José Luís Güntzel:
A low-power configurable VLSI architecture for sum of absolute differences calculation. 1-4 - Marcos Santana Farias, Nadia Nedjah, Luiza de Macedo Mourelle:
Efficient hardware architecture for embedded radionuclide identification. 1-4 - Satyanarayana Telikepalli, Sang Kyu Kim, Sung Joo Park, Madhavan Swaminathan, Youkeun Han:
Managing signal and power integrity using power transmission lines and alternative signaling schemes. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-28 22:12 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
