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2010 – 2019
- 2018
[c9]João G. Nizer Rahmeier
, Eduardo A. C. da Costa, Alessandro Girardi, Sidinei Ghissoni:
Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication. SBCCI 2018: 1-6- 2015
- [c8]Sidinei Ghissoni, Eduardo Costa, Ricardo Reis:
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. PATMOS 2015: 169-176 - 2014
- [c7]Sidinei Ghissoni, Eduardo A. C. da Costa, Angelo Goncalves da Luz:
Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors. VLSI-SoC 2014: 1-6 - 2013
- [c6]João G. Nizer Rahmeier, Angelo G. da Luz, Eduardo A. C. da Costa, Sidinei Ghissoni:
Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm. ICECS 2013: 33-36 - [c5]Angelo Goncalves da Luz, Eduardo A. C. da Costa, Sidinei Ghissoni:
Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms. LASCAS 2013: 1-4 - 2012
- [c4]Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Efficient area and power multiplication part of FFT based on twiddle factor decomposition. ICECS 2012: 657-660 - 2011
- [c3]Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ICECS 2011: 567-570 - 2010
- [c2]Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis:
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS 2010: 859-862
2000 – 2009
- 2009
- [c1]Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro:
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. PATMOS 2009: 297-306
Coauthor Index
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