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ORCIDMarc Pons 0001
Person information
- affiliation: Swiss Center for Electronics and Microtechnology (CSEM), Neuchâtel, Switzerland
- affiliation (former, PhD 2012): Polytechnic University of Catalonia, Department of Electronic Engineering, Barcelona, Spain
Other persons with the same name
- Marc Pons 0002
![[0000-0001-9105-0772]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-9105-0772")
— Andorra Research + Innovation, Sant Julià de Lòria, Andorra (and 2 more)
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2020 – today
- 2022
[j1]Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini:
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. ACM Trans. Embed. Comput. Syst. 21(5): 56:1-56:36 (2022)- 2021
- [c16]Komail M. H. Badami, Marc Pons Solé, Erfan Azarkhish, André Fivaz, Michaël Rapin, Olivier Chételat, Stéphane Emery:
Single-Battery Cooperative Sensors For Multi-Lead Long Term Ambulatory ECG Measurement. BioCAS 2021: 1-4 - [c15]Enric M. Calvo, Philippe Renevey, Mathieu Lemay, Andrea Bonetti, Marc Pons Solé, Régis Cattenoz, Stéphane Emery, Ricard Delgado-Gonzalo:
Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs. EMBC 2021: 6978-6981 - [i1]Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini:
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. CoRR abs/2106.12810 (2021)
2010 – 2019
- 2019
- [c14]Marc Pons, Christoph Thomas Müller, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi:
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. CICC 2019: 1-4 - [c13]Marc Pons Solé, Andre Bischof, Lorenzo Bergamini, Philippe Dallemagne, Stéphane Emery, Komail M. H. Badami, Jiang Deng, Themistoklis Mavrogordatos, Erfan Azarkhish, Loïc Zahnd, Costantino Cosentino, Marcin K. Augustyniak, Yingyun Zha:
A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control. ESSCIRC 2019: 73-76 - [c12]Lorenzo Bergamini, Marc Pons Solé, Jean-Dominique Decotignie, Philippe Dallemagne:
WiseTOP: a quality of service-aware low power acquisition and wireless communication platform for prosthesis control. ICECS 2019: 879-882 - [c11]Jian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons, David Ruffieux, Claude Arm, Pascal Persechini, Stéphane Emery:
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. ISLPED 2019: 1-4 - [c10]Christoph Thomas Müller, Marc Pons, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi:
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC. PRIME 2019: 285-288 - 2017
- [c9]Pierre-François Rüedi, A. Bishof, Marcin K. Augustyniak, Pascal Persechini, Jean-Luc Nagel, Marc Pons, Stéphane Emery, Olivier Chételat:
Ultra low power microelectronics for wearable and medical devices. DATE 2017: 1426-1431 - 2016
- [c8]Marc Pons, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stéphane Emery:
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. ESSCIRC 2016: 41-44 - 2015
- [c7]Christian Piguet, Marc Pons, Daniel Séverac:
Sub-Threshold Design and Architectural Choices. ISVLSI 2015: 481-484 - 2013
- [c6]Marc Pons, Jean-Luc Nagel, Daniel Séverac, Marc-Nicolas Morgan, Daniel Sigg, Pierre-François Rüedi, Christian Piguet:
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. PATMOS 2013: 9-15 - 2012
- [c5]Marc Pons, Marc-Nicolas Morgan, Christian Piguet:
Fixed origin corner square inspection layout regularity metric. DATE 2012: 1397-1402 - [c4]Marc Pons, Jean-Luc Nagel, Christian Piguet:
Maximum delay variation temperature-aware standard cell design. ICECS 2012: 296-299 - 2011
- [c3]Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
Design of complex circuits using the Via-Configurable transistor array regular layout fabric. SoCC 2011: 166-169 - 2010
- [c2]Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
VCTA: A Via-Configurable Transistor Array regular fabric. VLSI-SoC 2010: 335-340
2000 – 2009
- 2007
- [c1]Dennis Andrade, Ferran Martorell, Marc Pons, Francesc Moll, Antonio Rubio:
Power supply noise and logic error probability. ECCTD 2007: 152-155
Coauthor Index
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