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ORCIDVladimir Rybalkin
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2020 – today
- 2022
[b1]Vladimir Rybalkin:
Efficient hardware accleration of recurrent neural networks = Effiziente Hardwarebeschleunigung rekurrenter neuronaler Netze. Kaiserslautern University of Technology, Germany, 2022, ISBN 978-3-95974-187-3, pp. 1-170- [j6]Vladimir Rybalkin, Jonas Ney, Menbere Kina Tekleyohannes, Norbert Wehn:
When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network. ACM Trans. Reconfigurable Technol. Syst. 15(1): 2:1-2:35 (2022) - 2021
- [j5]Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Javier Alejandro Varela, Norbert Wehn, Andreas Dengel:
iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing. Int. J. Parallel Program. 49(2): 253-284 (2021) - [j4]Menbere Kina Tekleyohannes
, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Javier Alejandro Varela, Norbert Wehn, Andreas Dengel:
iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing. J. Imaging 7(9): 175 (2021) - [j3]Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng:
Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 93(12): 1467 (2021) - [c10]Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger, Norbert Wehn:
HALF: Holistic Auto Machine Learning for FPGAs. FPL 2021: 363-368 - [c9]Iris Walter, Jonas Ney, Tim Hotfilter, Vladimir Rybalkin, Julian Höfer, Norbert Wehn, Jürgen Becker:
Embedded Face Recognition for Personalized Services in the Assistive Robotics. PKDD/ECML Workshops (1) 2021: 339-350 - [i2]Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger, Norbert Wehn:
HALF: Holistic Auto Machine Learning for FPGAs. CoRR abs/2106.14771 (2021) - 2020
- [j2]Mhd Rashed Al Koutayni, Vladimir Rybalkin, Jameel Malik, Ahmed Elhayek, Christian Weis, Gerd Reis, Norbert Wehn, Didier Stricker:
Real-Time Energy Efficient Hand Pose Estimation: A Case Study. Sensors 20(10): 2828 (2020) - [j1]Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng:
Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 92(11): 1219-1245 (2020) - [c8]Vladimir Rybalkin, Norbert Wehn:
When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network. FPGA 2020: 111-121
2010 – 2019
- 2019
- [c7]Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn:
An In-DRAM Neural Network Processing Engine. ISCAS 2019: 1-5 - [c6]Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn, Andreas Dengel:
iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction. ReConFig 2019: 1-8 - 2018
- [c5]Vladimir Rybalkin, Syed Saqib Bukhari, Muhammad Mohsin Ghaffar, Aqib Ghafoor, Norbert Wehn, Andreas Dengel:
iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization. DocEng 2018: 24:1-24:8 - [c4]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott:
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. FPL 2018: 89-96 - [i1]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott:
FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs. CoRR abs/1807.04093 (2018) - 2017
- [c3]Vladimir Rybalkin, Norbert Wehn, Mohammad Reza Yousefi, Didier Stricker:
Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition. DATE 2017: 1390-1395 - 2016
- [c2]Vladimir Rybalkin, Philipp Schläfer, Norbert Wehn:
A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256). VTC Spring 2016: 1-5 - 2015
- [c1]Philipp Schläfer, Vladimir Rybalkin, Norbert Wehn, Matthias Alles, Timo Lehnigk-Emden, Emmanuel Boutillon:
A new architecture for high throughput, low latency NB-LDPC check node processing. PIMRC 2015: 1392-1397
Coauthor Index
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