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2020 – today
- 2024
[c9]Ning-Chi Huang, Chi-Chih Chang, Wei-Cheng Lin, Endri Taka, Diana Marculescu, Kai-Chiang Wu:
ELSA: Exploiting Layer-wise N: M Sparsity for Vision Transformer Acceleration. CVPR Workshops 2024: 8006-8015- [c8]Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu
, Kai-Chiang Wu:
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. WACV 2024: 2470-2479 - [i3]Chi-Chih Chang, Wei-Cheng Lin, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Kai-Chiang Wu:
Palu: Compressing KV-Cache with Low-Rank Projection. CoRR abs/2407.21118 (2024) - [i2]Ning-Chi Huang, Chi-Chih Chang, Wei-Cheng Lin, Endri Taka, Diana Marculescu, Kai-Chiang Wu:
ELSA: Exploiting Layer-wise N:M Sparsity for Vision Transformer Acceleration. CoRR abs/2409.09708 (2024) - 2023
- [c7]Ning-Chi Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu:
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators. ISQED 2023: 1-8 - [i1]Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu:
FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. CoRR abs/2311.03912 (2023) - 2022
- [j1]Ning-Chi Huang, Chao-Wei Cheng, Kai-Chiang Wu:
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 81-94 (2022) - 2021
- [c6]Samuel Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, M.-H. Yang, Kai-Chiang Wu:
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. VLSI-DAT 2021: 1-7 - [c5]Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu:
An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention. VTS 2021: 1-7 - 2020
- [c4]Shu-Ming Liu, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, Kai-Chiang Wu:
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator. VLSI-DAT 2020: 1-3
2010 – 2019
- 2019
- [c3]Ning-Chi Huang, Szu-Ying Chen, Kai-Chiang Wu:
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications. DATE 2019: 692-697 - [c2]Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu:
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. ISVLSI 2019: 218-223 - 2017
- [c1]Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu:
Analysis and optimization of variable-latency designs in the presence of timing variability. DATE 2017: 1219-1224
Coauthor Index
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