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ORCIDEnrico Reggiani
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2020 – today
- 2024
[b1]Enrico Reggiani:
Efficient hardware acceleration of deep neural networks via arithmetic complexity reduction. Polytechnic University of Catalonia, Spain, 2024- 2023
- [j2]Francesco Minervini
, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal:
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. ACM Trans. Archit. Code Optim. 20(2): 28:1-28:25 (2023) - [c15]Enrico Reggiani, Renzo Andri, Lukas Cavigelli:
Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation. DAC 2023: 1-6 - [c14]Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa:
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. DCIS 2023: 1-6 - [c13]Enrico Reggiani, Alessandro Pappalardo, Max Doblas, Miquel Moretó, Mauro Olivieri, Osman Sabri Unsal, Adrián Cristal:
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices. HPCA 2023: 1085-1098 - [i2]Enrico Reggiani, Renzo Andri, Lukas Cavigelli:
Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation. CoRR abs/2305.04546 (2023) - 2022
- [c12]Enrico Reggiani, Cristóbal Ramírez Lazo, Roger Figueras Bagué, Adrián Cristal, Mauro Olivieri, Osman Sabri Unsal:
BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge. ASPLOS 2022: 56-69 - [c11]Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa:
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. DCIS 2022: 1-6 - [c10]Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis A. Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal:
Adaptable Register File Organization for Vector Processors. HPCA 2022: 786-799 - 2021
- [j1]Enrico Reggiani, Emanuele Del Sozzo, Davide Conficconi, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio:
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components. ACM Trans. Reconfigurable Technol. Syst. 14(3): 15:1-15:33 (2021) - [i1]Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis Alfonso Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal:
Adaptable Register File Organization for Vector Processors. CoRR abs/2111.05301 (2021) - 2020
- [c9]Nils Voss, Tobias Becker, Simon Tilbury, Georgi Gaydadjiev, Oskar Mencer, Anna Maria Nestorov, Enrico Reggiani, Wayne Luk:
Performance Portable FPGA Design. FPGA 2020: 324
2010 – 2019
- 2019
- [c8]Anna Maria Nestorov, Alberto Scolari, Enrico Reggiani, Luca Stornaiuolo, Marco D. Santambrogio:
A Case Study for an Accelerated DCNN on FPGA-Based Embedded Distributed System. IPDPS Workshops 2019: 91-94 - [c7]Enrico Reggiani, Marco Rabozzi, Anna Maria Nestorov, Alberto Scolari, Luca Stornaiuolo, Marco D. Santambrogio:
Pareto Optimal Design Space Exploration for Accelerated CNN on FPGA. IPDPS Workshops 2019: 107-114 - 2018
- [c6]Enrico Reggiani, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio:
An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils. IPDPS Workshops 2018: 115-122 - 2017
- [c5]Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev:
From exaflop to exaflow. DATE 2017: 404-409 - [c4]Andrea Purgato, Enrico Reggiani, Eleonora D'Arnese, Tanya Y. Berger-Wolf, Marco Grimaldi, Gianluca Durelli, Marco D. Santambrogio:
GPU-based computation for brain spatio-temporal networks definition. EMBC 2017: 1493-1496 - [c3]Anna Maria Nestorov, Enrico Reggiani, Hristina Palikareva, Pavel Burovskiy, Tobias Becker, Marco D. Santambrogio:
A Scalable Dataflow Implementation of Curran's Approximation Algorithm. IPDPS Workshops 2017: 150-157 - [c2]Enrico Reggiani, Eleonora D'Arnese, Andrea Purgato, Marco D. Santambrogio:
Pearson Correlation Coefficient Acceleration for Modeling and Mapping of Neural Interconnections. IPDPS Workshops 2017: 223-228 - 2016
- [c1]Giulia Guidi, Enrico Reggiani, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott, Marco D. Santambrogio:
On How to Improve FPGA-Based Systems Design Productivity via SDAccel. IPDPS Workshops 2016: 247-252
Coauthor Index
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