"Process variation in embedded memories: failure analysis and variation ..."

Amit Agarwal et al. (2005)

> Home

Details and statistics

DOI: 10.1109/JSSC.2005.852159

access: closed

type: Journal Article

metadata version: 2022-03-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/AgarwalPMR05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/AgarwalPMR05
Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy:
Process variation in embedded memories: failure analysis and variation aware architecture. IEEE J. Solid State Circuits 40(9): 1804-1814 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.