"A noise tolerant cache design to reduce gate and sub-threshold leakage in ..."

Amit Agarwal, Kaushik Roy (2003)

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DOI: 10.1145/871506.871514

access: closed

type: Conference or Workshop Paper

metadata version: 2019-07-17

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  - conf/islped/AgarwalR03
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  - https://dblp.org/rec/conf/islped/AgarwalR03
Amit Agarwal, Kaushik Roy:
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ISLPED 2003: 18-21

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