"A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for ..."

Patrick Ndai, Ashish Goel, Kaushik Roy (2010)

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DOI: 10.1109/TVLSI.2009.2022628

access: closed

type: Journal Article

metadata version: 2020-03-11

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Patrick Ndai, Ashish Goel, Kaushik Roy:
A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1209-1219 (2010)

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