"Multiple Scan Chain Design Technique for Power Reduction during Test ..."

Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy (2003)

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DOI: 10.1109/DFTVS.2003.1250112

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy:
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198

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