"Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique."

Priya Patil et al. (1997)

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DOI: 10.1109/ICVD.1997.568073

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy:
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. VLSI Design 1997: 179-184

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