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2020 – today
- 2020
[c69]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. ISCAS 2020: 1-5- [i3]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. CoRR abs/2005.06318 (2020)
2010 – 2019
- 2019
- [j26]Charlotte Frenkel
, Martin Lefebvre, Jean-Didier Legat, David Bol:
A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS. IEEE Trans. Biomed. Circuits Syst. 13(1): 145-158 (2019) - [j25]Charlotte Frenkel, Jean-Didier Legat, David Bol:
MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning. IEEE Trans. Biomed. Circuits Syst. 13(5): 999-1010 (2019) - [c68]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. ISCAS 2019: 1-5 - [i2]Charlotte Frenkel, Jean-Didier Legat, David Bol:
MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. CoRR abs/1904.08513 (2019) - 2018
- [i1]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS. CoRR abs/1804.07858 (2018) - 2017
- [c67]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors. BioCAS 2017: 1-4 - [c66]Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol:
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. ISCAS 2017: 1-4 - 2016
- [j24]Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol:
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. 57: 76-86 (2016) - [c65]Charlotte Frenkel, Jean-Didier Legat, David Bol:
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. VLSI-SoC 2016: 1-6 - 2015
- [c64]Charlotte Frenkel, Jean-Didier Legat, David Bol:
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. ReCoSoC 2015: 1-7 - 2014
- [j23]Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville:
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. 10(1): 118-126 (2014) - [j22]François Botman, David Bol, Jean-Didier Legat, Kaushik Roy:
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2561-2570 (2014) - [c63]François Botman, Julien De Vos, Sebastien Bernard, François Stas, Jean-Didier Legat, David Bol:
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. ISCAS 2014: 1207-1210 - [c62]Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol:
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS 2014: 1-7 - 2013
- [j21]David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat:
SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. IEEE J. Solid State Circuits 48(1): 20-32 (2013) - [c61]Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat:
An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT 2013: 9-12 - 2012
- [j20]Angelo Kuti Lusala, Jean-Didier Legat:
Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks. Int. J. Reconfigurable Comput. 2012: 474765:1-474765:16 (2012) - [j19]Angelo Kuti Lusala, Jean-Didier Legat:
A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks. ACM Trans. Reconfigurable Technol. Syst. 5(3): 15:1-15:22 (2012) - [c60]David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat:
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. ISSCC 2012: 490-492 - [c59]Angelo Kuti Lusala, Jean-Didier Legat:
A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications. NEWCAS 2012: 17-20 - [c58]Renaud Van Langendonck, Angelo Kuti Lusala, Jean-Didier Legat:
MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs. ReCoSoC 2012: 1-8 - 2011
- [j18]Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert:
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. J. Cryptogr. Eng. 1(1): 79-86 (2011) - [c57]Angelo Kuti Lusala, Jean-Didier Legat:
Combining sdm-based circuit switching with packet switching in a NoC for real-time applications. ISCAS 2011: 2505-2508 - [c56]Angelo Kuti Lusala, Jean-Didier Legat:
A SDM-TDM based circuit-switched router for on-chip networks. ReCoSoC 2011: 1-8 - [c55]Daniel Vergeylen, Angelo Kuti Lusala, Jean-Didier Legat:
A new mechanism to reduce congestion on TDM networks-on-chips. ReCoSoC 2011: 1-8 - 2010
- [j17]Ilham Hassoune, Denis Flandre, Ian O'Connor, Jean-Didier Legat:
ULPFA: A New Efficient Design of a Power-Aware Full Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 2066-2074 (2010) - [j16]David Bol, Denis Flandre, Jean-Didier Legat:
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. ACM Trans. Design Autom. Electr. Syst. 16(1): 2:1-2:26 (2010) - [c54]Bertrand Rousseau, Philippe Manet, Igor Loiselle, Jean-Didier Legat, Hans Vandierendonck:
A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms. DASIP 2010: 273-280 - [c53]David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat:
The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. ESSCIRC 2010: 522-525 - [c52]David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat:
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. ISCAS 2010: 1484-1487 - [c51]Angelo Kuti Lusala, Jean-Didier Legat:
Combining circuit and packet switching with bus architecture in a NoC for real-time applications. ISCAS 2010: 2880-2883 - [c50]Angelo Kuti Lusala, Jean-Didier Legat:
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks. ReConFig 2010: 340-345
2000 – 2009
- 2009
- [j15]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Interests and Limitations of Technology Scaling for Subthreshold Logic. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1508-1519 (2009) - [c49]David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat:
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ISLPED 2009: 3-8 - [c48]David Bol, Denis Flandre, Jean-Didier Legat:
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. ISLPED 2009: 21-26 - [c47]Lotfi Guedria, Damien Hubaux, Mathieu Ocaña, Jean-Didier Legat:
Flexible embedded system for sensor integration and custom data processing in an automotive application. IWCMC 2009: 1304-1309 - 2008
- [j14]Philippe Manet, Daniel Maufroid, Leonardo Tosi, Grégory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba, Pol Cuvelier, Bertrand Rousseau, Paul Gelineau:
An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications. EURASIP J. Embed. Syst. 2008 (2008) - [c46]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Analysis and minimization of practical energy in 45nm subthreshold logic circuits. ICCD 2008: 294-300 - [c45]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Impact of Technology Scaling on Digital Subthreshold Circuits. ISVLSI 2008: 179-184 - 2007
- [j13]Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat:
Dynamic differential self-timed logic families for robust and low-power security ICs. Integr. 40(3): 355-364 (2007) - [j12]David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat:
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. J. Multiple Valued Log. Soft Comput. 13(1-2): 61-78 (2007) - [c44]Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat:
By-passing the out-of-order execution pipeline to increase energy-efficiency. Conf. Computing Frontiers 2007: 97-104 - [c43]Bertrand Rousseau, Philippe Manet, D. Galerin, D. Merkenbreack, Jean-Didier Legat, F. Dedeken, Yves Gabriel:
Enabling certification for dynamic partial reconfiguration using a minimal flow. DATE 2007: 983-988 - [c42]Philippe Manet, Daniel Maufroid, Leonardo Tosi, Marco Di Ciano, Olivier Mulertt, Yves Gabriel, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba:
Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics. DATE 2007: 994-999 - [c41]Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat:
NoC Implementation in FPGA Using Torus Topology. FPL 2007: 778-781 - [c40]David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat:
Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices. ICECS 2007: 1404-1407 - 2006
- [j11]Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, Jean-Didier Legat:
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. J. Low Power Electron. 2(1): 95-104 (2006) - [j10]Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat:
Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. Microelectron. J. 37(9): 997-1006 (2006) - [j9]Antonin Descampe, François-Olivier Devaux, Gaël Rouvroy, Jean-Didier Legat, Jean-Jacques Quisquater, Benoît Macq:
A Flexible Hardware JPEG 2000 Decoder for Digital Cinema. IEEE Trans. Circuits Syst. Video Technol. 16(11): 1397-1410 (2006) - [c39]Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat:
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. ASAP 2006: 347-353 - [c38]Hans Vandierendonck, Philippe Manet, Jean-Didier Legat:
Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. DATE 2006: 357-362 - [c37]David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo:
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS 2006: 1049-1052 - 2005
- [c36]François-Xavier Standaert, Frédéric Lefèbvre, Gaël Rouvroy, Benoît Macq, Jean-Jacques Quisquater, Jean-Didier Legat:
Practical Evaluation of a Radial Soft Hash Algorithm. ITCC (2) 2005: 89-94 - [c35]Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat:
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. PATMOS 2005: 19-29 - [c34]François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. PATMOS 2005: 550-560 - 2004
- [c33]Gaël Rouvroy, François-Xavier Standaert, Frédéric Lefèbvre, Jean-Jacques Quisquater, Benoît Macq, Jean-Didier Legat:
Reconfigurable hardware solutions for the digital rights management of digital cinema. Digital Rights Management Workshop 2004: 40-53 - [c32]Gaël Rouvroy, Frédéric Lefèbvre, François-Xavier Standaert, Benoît Macq, Jean-Jacques Quisquater, Jean-Didier Legat:
Hardware implementation of a fingerprinting algorithm suited for digital cinema. EUSIPCO 2004: 1497-1500 - [c31]Antonin Descampe, François-Olivier Devaux, Gaël Rouvroy, Benoît Macq, Jean-Didier Legat:
An efficient FPGA implementation of a flexible JPEG2000 decoder for Digital Cinema. EUSIPCO 2004: 2019-2022 - [c30]François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat:
ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware. FSE 2004: 279-299 - [c29]Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications. ITCC (2) 2004: 583-587 - [c28]Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre:
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. PATMOS 2004: 189-197 - 2003
- [j8]Elias N. Malamas, Euripides G. M. Petrakis, Michalis E. Zervakis, Laurent Petit, Jean-Didier Legat:
A survey on industrial vision systems, applications, tools. Image Vis. Comput. 21(2): 171-188 (2003) - [j7]Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis. IEEE Trans. Computers 52(4): 473-482 (2003) - [j6]Grégory Dillen, Benoît Georis, Olivier Cantineau, Jean-Didier Legat:
Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 13(9): 944-950 (2003) - [c27]François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat:
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. CHES 2003: 334-350 - [c26]François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat:
A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. FPGA 2003: 216-224 - [c25]Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES. FPGA 2003: 247 - [c24]Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. FPL 2003: 181-193 - [c23]Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
Efficient FPGA Implementation of Block Cipher MISTY1. IPDPS 2003: 185 - 2002
- [c22]François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat:
A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results. CHES 2002: 593-609 - [c21]Frédéric Lefèbvre, Benoît Macq, Jean-Didier Legat:
RASH: RAdon soft hash algorithm. EUSIPCO 2002: 1-4 - [c20]Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat:
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. FPL 2002: 780-789 - [c19]François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat:
An FPGA Implementation of the Linear Cryptanalysis. FPL 2002: 845-852 - 2001
- [c18]Jean-Pierre David, Tony Postiau, Paul Fisette, Jean-Didier Legat:
Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. IPDPS 2001: 143 - 2000
- [j5]Pierre Desneux, Jean-Didier Legat:
A dedicated DSP architecture for discrete wavelet transform. Integr. Comput. Aided Eng. 7(2): 135-153 (2000)
1990 – 1999
- 1999
- [c17]Xavier Verians, Jean-Didier Legat, Jean-Jacques Quisquater, Benoît Macq:
A New Parallelism Management Scheme for Multiprocessor Systems. ACPC 1999: 246-256 - [c16]Tanguy Gilmont, Jean-Didier Legat, Jean-Jacques Quisquater:
Enhancing Security in the Memory Management Unit. EUROMICRO 1999: 1449- - [c15]Xavier Verians, Jean-Didier Legat, Jean-Jacques Quisquater, Benoît Macq:
A Graph-Oriented Task Manager for Small Multiprocessor Systems. Euro-Par 1999: 735-744 - [c14]Tony Postiau, Paul Fisette, Jean-Didier Legat:
Fine grain parallelization of multibody system equations of motion. PARCO 1999: 193-200 - [c13]Tanguy Gilmont, Jean-Didier Legat, Jean-Jacques Quisquater:
Architecture of security management unit for safe hosting of multiple agents. Security and Watermarking of Multimedia Contents 1999: 472-483 - 1998
- [j4]Emmanuel Hanssens, Bertrand Chupeau, Jean-Didier Legat, Benoît Macq:
Selective prediction error transmission using motion information. Signal Process. Image Commun. 12(1): 71-81 (1998) - [j3]C. Amerijckx, Michel Verleysen, Philippe Thissen, Jean-Didier Legat:
Image compression by self-organized Kohonen map. IEEE Trans. Neural Networks 9(3): 503-507 (1998) - [j2]Olivier Cantineau, Laurent Petit, Jean-Didier Legat:
Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit. J. VLSI Signal Process. 20(3): 251-265 (1998) - [c12]Olivier Cantineau, Jean-Didier Legat:
Efficient Parallelisation of an MPEG-2 Codec on a TMS320C80 Video Processor. ICIP (3) 1998: 977-980 - [c11]Jean-Pierre David, Jean-Didier Legat:
A Data-Flow Oriented Co-Design for Reconfigurable Systems. International Workshop on Rapid System Prototyping 1998: 207-211 - 1996
- [c10]Tanguy Gilmont, Xavier Verians, Jean-Didier Legat, Claude Veraart:
Resolution reduction by growth of zones for visual prosthesis. ICIP (1) 1996: 299-302 - 1995
- [c9]Jean-Luc Voz, Michel Verleysen, Philippe Thissen, Jean-Didier Legat:
Suboptimal Bayesian classification by vector quantization with small clusters. ESANN 1995 - [c8]Michel Verleysen, Jean-Luc Voz, Philippe Thissen, Jean-Didier Legat:
A statistical neural network for high-dimensional vector classification. ICNN 1995: 990-994 - [c7]Jean-Luc Voz, Michel Verleysen, Philippe Thissen, Jean-Didier Legat:
A Practical View of Suboptimal Bayesian Classification with Radial Gaussian Kernels. IWANN 1995: 404-411 - [c6]Philippe Thissen, Michel Verleysen, Jean-Didier Legat, Jordi Madrenas, Jordi Domínguez:
A VLSI System for Neural Bayesian and LVQ Classification. IWANN 1995: 696-703 - [c5]Philippe Thissen, Michel Verleysen, Jean-Didier Legat:
An Associative Processor Dedicated to Classification by Neural Methods. IWANN 1995: 704-711 - 1993
- [j1]Damien Macq, Michel Verleysen, Paul G. A. Jespers, Jean-Didier Legat:
Analog implementation of a Kohonen map with on-chip learning. IEEE Trans. Neural Networks 4(3): 456-461 (1993) - [c4]Michel Verleysen, Philippe Thissen, Jean-Didier Legat:
Optimal decision surfaces in LVQ1 classiffication of patterns. ESANN 1993 - [c3]Michel Verleysen, Philippe Thissen, Jean-Didier Legat:
Linear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns. IWANN 1993: 340-345 - [c2]Pierre Desneux, Jean-Didier Legat, Benoît Macq, Jean-Yves Mertès:
Systolic implementation of a bidimensional lattice filter bank for multiresolution image coding. VCIP 1993 - 1992
- [c1]Jean-Didier Legat, J. P. Cornil, Damien Macq, Michel Verleysen:
A real-time VLSI-based architecture for multi-motion estimation. ICPR (4) 1992: 147-150
Coauthor Index
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