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Journal Articles
- 2020
[j105]Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa:
Universal Testing for Linear Feed-Forward/Feedback Shift Registers. IEICE Trans. Inf. Syst. 103-D(5): 1023-1030 (2020)- 2018
- [j104]Dong Xiang, Krishnendu Chakrabarty
, Hideo Fujiwara:
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. ACM Trans. Design Autom. Electr. Syst. 23(6): 73:1-73:23 (2018) - 2017
- [j103]Hideo Fujiwara, Katsuya Fujiwara:
Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents. IEICE Trans. Inf. Syst. 100-D(9): 2232-2236 (2017) - 2016
- [j102]Hideo Fujiwara, Katsuya Fujiwara:
Properties of Generalized Feedback Shift Registers for Secure Scan Design. IEICE Trans. Inf. Syst. 99-D(4): 1255-1258 (2016) - [j101]Hideo Fujiwara, Katsuya Fujiwara:
Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design. IEICE Trans. Inf. Syst. 99-D(8): 2182-2185 (2016) - [j100]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip. IEEE Trans. Computers 65(9): 2767-2779 (2016) - 2015
- [j99]Debesh Kumar Das, Hideo Fujiwara:
One More Class of Sequential Circuits having Combinational Test Generation Complexity. J. Electron. Test. 31(3): 321-327 (2015) - [j98]Hideo Fujiwara, Katsuya Fujiwara:
Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers. IEICE Trans. Inf. Syst. 98-D(10): 1852-1855 (2015) - 2013
- [j97]Katsuya Fujiwara, Hideo Fujiwara:
Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design. IEICE Trans. Inf. Syst. 96-D(5): 1125-1133 (2013) - [j96]Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto:
Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents. IPSJ Trans. Syst. LSI Des. Methodol. 6: 27-33 (2013) - 2012
- [j95]Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara:
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. 28(4): 511-521 (2012) - [j94]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara:
Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. 95-D(12): 3001-3009 (2012) - [j93]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1951-1959 (2012) - 2011
- [j92]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. 27(2): 99-108 (2011) - [j91]Chia Yee Ooi, Hideo Fujiwara:
A New Design-for-Testability Method Based on Thru-Testability. J. Electron. Test. 27(5): 583-598 (2011) - [j90]Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
F-Scan: A DFT Method for Functional Scan at RTL. IEICE Trans. Inf. Syst. 94-D(1): 104-113 (2011) - [j89]Katsuya Fujiwara, Hideo Fujiwara, Hideo Tamamoto:
Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design. IEICE Trans. Inf. Syst. 94-D(7): 1430-1439 (2011) - 2010
- [j88]Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara:
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. J. Electron. Test. 26(2): 151-164 (2010) - [j87]Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. IEICE Trans. Inf. Syst. 93-D(1): 24-32 (2010) - [j86]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. 93-D(6): 1549-1559 (2010) - [j85]Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara:
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. 93-D(7): 1857-1865 (2010) - 2008
- [j84]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. 91-D(3): 736-746 (2008) - [j83]Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Trans. Inf. Syst. 91-D(3): 747-755 (2008) - [j82]Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara:
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Trans. Inf. Syst. 91-D(3): 763-770 (2008) - [j81]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. 91-D(3): 807-814 (2008) - [j80]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Trans. Inf. Syst. 91-D(7): 1999-2007 (2008) - [j79]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Trans. Inf. Syst. 91-D(7): 2008-2017 (2008) - [j78]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. 91-D(10): 2440-2448 (2008) - [j77]Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 999-1012 (2008) - [j76]Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1535-1544 (2008) - 2007
- [j75]Ilia Polian, Hideo Fujiwara:
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. J. Electron. Test. 23(5): 445-455 (2007) - [j74]Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara:
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. 90-D(1): 296-305 (2007) - [j73]Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara:
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation. IEICE Trans. Inf. Syst. 90-D(8): 1202-1212 (2007) - [j72]Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara:
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. IEEE Trans. Computers 56(4): 557-562 (2007) - [j71]Dong Xiang, Mingjing Chen, Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56(12): 1619-1628 (2007) - [j70]Dong Xiang, Kaiwei Li, Hideo Fujiwara, Krishnaiyan Thulasiraman, Jiaguang Sun:
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 450-454 (2007) - [j69]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 790-800 (2007) - 2006
- [j68]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Trans. Inf. Syst. 89-D(3): 1165-1172 (2006) - [j67]Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara:
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Trans. Inf. Syst. 89-D(4): 1490-1497 (2006) - [j66]Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara:
A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Trans. Inf. Syst. 89-D(6): 1931-1939 (2006) - [j65]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
Effect of BIST Pretest on IC Defect Level. IEICE Trans. Inf. Syst. 89-D(10): 2626-2636 (2006) - [j64]Tomokazu Yoneda, Hideo Fujiwara:
Design for consecutive transparency method of RTL circuits. Syst. Comput. Jpn. 37(2): 1-10 (2006) - [j63]Erik Larsson, Hideo Fujiwara:
System-on-chip test scheduling with reconfigurable core wrappers. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 305-309 (2006) - [j62]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1203-1215 (2006) - 2005
- [j61]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode. IEICE Trans. Inf. Syst. 88-D(3): 610-618 (2005) - [j60]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST. IEICE Trans. Inf. Syst. 88-D(6): 1210-1216 (2005) - [j59]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Trans. Inf. Syst. 88-D(8): 1940-1947 (2005) - [j58]Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara:
Classification of Sequential Circuits Based on tauk Notation and Its Applications. IEICE Trans. Inf. Syst. 88-D(12): 2738-2747 (2005) - [j57]Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
Improving test effectiveness of scan-based BIST by scan chain partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 916-927 (2005) - 2004
- [j56]Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian:
Design & Test Education in Asia. IEEE Des. Test Comput. 21(4): 331-338 (2004) - [j55]Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electron. Test. 20(3): 315-323 (2004) - [j54]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Trans. Inf. Syst. 87-D(3): 609-619 (2004) - [j53]Erik Larsson, Hideo Fujiwara:
Preemptive System-on-Chip Test Scheduling. IEICE Trans. Inf. Syst. 87-D(3): 620-629 (2004) - [j52]Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng:
Efficient test solutions for core-based designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 758-775 (2004) - 2003
- [j51]Dong Xiang, Yi Xu, Hideo Fujiwara:
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. IEEE Trans. Computers 52(8): 1063-1075 (2003) - 2002
- [j50]Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electron. Test. 18(1): 55-62 (2002) - [j49]Tomokazu Yoneda, Hideo Fujiwara:
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. J. Electron. Test. 18(4-5): 487-501 (2002) - [j48]Yoshiaki Katayama, Eiichiro Ueda, Hideo Fujiwara, Toshimitsu Masuzawa:
A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings. J. Parallel Distributed Comput. 62(5): 865-884 (2002) - [j47]Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A layout adjustment problem for disjoint rectangles preserving orthogonal order. Syst. Comput. Jpn. 33(2): 31-42 (2002) - [j46]Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara:
A nonscan DFT method for controllers to provide complete fault efficiency. Syst. Comput. Jpn. 33(5): 64-75 (2002) - [j45]Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara:
Test sequence compaction methods for acyclic sequential circuits using a time expansion model. Syst. Comput. Jpn. 33(10): 105-115 (2002) - [j44]Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
Parallel algorithms for selection on the BSP and BSP* models. Syst. Comput. Jpn. 33(12): 97-107 (2002) - [j43]Dong Xiang, Hideo Fujiwara:
Handling the pin overhead problem of DFTs for high-quality and at-speed tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1105-1113 (2002) - [j42]Emil Gizdarski, Hideo Fujiwara:
SPIRIT: a highly robust combinational test generation algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1446-1458 (2002) - 2001
- [j41]Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A causal broadcast protocol for distributed mobile systems. Syst. Comput. Jpn. 32(3): 65-75 (2001) - 2000
- [j40]Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara:
LFSR-Based Deterministic TPG for Two-Pattern Testing. J. Electron. Test. 16(5): 419-426 (2000) - [j39]Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara:
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. J. Electron. Test. 16(5): 553-566 (2000) - [j38]Hideo Fujiwara:
A New Class of Sequential Circuits with Combinational Test Generation Complexity. IEEE Trans. Computers 49(9): 895-905 (2000) - 1999
- [j37]Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A cost optimal parallel algorithm for weighted distance transforms. Parallel Comput. 25(4): 405-416 (1999) - 1998
- [j36]Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara:
Universal Fault Diagnosis for Lookup Table FPGAs. IEEE Des. Test Comput. 15(1): 39-44 (1998) - [j35]Hideo Fujiwara:
Needed: Third-generation ATPG Benchmarks. IEEE Des. Test Comput. 15(1): 96- (1998) - [j34]Michiko Inoue, Hideo Fujiwara:
An approach to test synthesis from higher level. Integr. 26(1-2): 101-116 (1998) - [j33]Hiroshi Youra, Tomoo Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
On the synthesis of synchronizable finite state machines with partial scan. Syst. Comput. Jpn. 29(1): 53-62 (1998) - [j32]Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara:
Partial scan design methods based on internally balanced structure. Syst. Comput. Jpn. 29(10): 26-35 (1998) - 1997
- [j31]Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara:
Parallel algorithms for connected-component problems of gray-scale images. Syst. Comput. Jpn. 28(1): 74-86 (1997) - [j30]Daisuke Yoshida, Toshimitsu Masuzawa, Hideo Fujiwara:
Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults. Syst. Comput. Jpn. 28(2): 33-43 (1997) - [j29]Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
Non-scan design for testable data paths using thru operation. Syst. Comput. Jpn. 28(10): 60-68 (1997) - [j28]Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki:
A sequential circuit structure with combinational test generation complexity and its application. Syst. Comput. Jpn. 28(11): 11-21 (1997) - 1995
- [j27]Hideo Fujiwara:
Foreword. IEICE Trans. Inf. Syst. 78-D(7): 789-790 (1995) - [j26]Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara:
An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images. Inf. Process. Lett. 54(5): 295-300 (1995) - [j25]Hideo Fujiwara, Tomoo Inoue:
Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System. IEEE Trans. Parallel Distributed Syst. 6(7): 677-686 (1995) - 1994
- [j24]Takayuki Fujino, Hideo Fujiwara:
A method of search space pruning based on search state dominance. Syst. Comput. Jpn. 25(4): 1-12 (1994) - 1993
- [j23]Takayuki Fujino, Hideo Fujiwara:
A Search Space Pruning Method for Test Pattern Generation using Search State Dominance. J. Circuits Syst. Comput. 3(4): 859- (1993) - [j22]Hideo Fujiwara, Akihiro Yamamoto:
Parity-scan design to reduce the cost of test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1604-1611 (1993) - 1990
- [j21]Hideo Fujiwara:
Computational Complexity of Controllability/Observability Problems for Combinational Circuits. IEEE Trans. Computers 39(6): 762-767 (1990) - [j20]Hideo Fujiwara, Tomoo Inoue:
Optimal granularity of test generation in a distributed system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 885-892 (1990) - 1989
- [j19]Hideo Fujiwara:
Enhancing random-pattern coverage of programmable logic arrays via masking technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9): 1022-1025 (1989) - 1988
- [j18]Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya:
Test research in Japan. IEEE Des. Test 5(5): 60-79 (1988) - [j17]Hideo Fujiwara:
A design of programmable logic arrays with random pattern-testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 5-10 (1988) - 1987
- [j16]Hideo Fujiwara:
A random-pattern testable design for programmable logic arrays. Syst. Comput. Jpn. 18(7): 95-102 (1987) - [j15]Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara:
A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. IEEE Trans. Computers 36(3): 369-373 (1987) - 1986
- [j14]Hideo Fujiwara:
Design for testability and built-in self-test for VLSI circuits. Microprocess. Microsystems 10(3): 139-147 (1986) - 1985
- [j13]Robert P. Treuer, Hideo Fujiwara, Vinod K. Agarwal:
Implementing a Built-In Self-Test PLA Design. IEEE Des. Test 2(2): 37-48 (1985) - 1984
- [j12]Akira Motohara, Hideo Fujiwara:
Design for Testability for Complete Test Coverage. IEEE Des. Test 1(4): 25-32 (1984) - [j11]Hideo Fujiwara:
A New PLA Design for Universal Testability. IEEE Trans. Computers 33(8): 745-750 (1984) - 1983
- [j10]Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara:
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. IEEE Trans. Computers 32(11): 1038-1046 (1983) - [j9]Hideo Fujiwara, Takeshi Shimono:
On the Acceleration of Test Generation Algorithms. IEEE Trans. Computers 32(12): 1137-1144 (1983) - 1982
- [j8]Hideo Fujiwara, Shunichi Toida:
The Complexity of Fault Detection Problems for Combinational Logic Circuits. IEEE Trans. Computers 31(6): 555-560 (1982) - 1981
- [j7]Hideo Fujiwara:
On Closedness and Test Complexity of Logic Circuits. IEEE Trans. Computers 30(8): 556-562 (1981) - [j6]Hideo Fujiwara, Kozo Kinoshita:
A Design of Programmable Logic Arrays with Universal Tests. IEEE Trans. Computers 30(11): 823-828 (1981) - 1978
- [j5]Hideo Fujiwara, Kozo Kinoshita:
Connection Assignments for Probabilistically Diagnosable Systems. IEEE Trans. Computers 27(3): 280-283 (1978) - [j4]Hideo Fujiwara, Kozo Kinoshita:
Some Existence Theorems for Probabilistically Diagnosable Systems. IEEE Trans. Computers 27(4): 379-384 (1978) - [j3]Hideo Fujiwara, Kozo Kinoshita:
On the Computational Complexity of System Diagnosis. IEEE Trans. Computers 27(10): 881-885 (1978) - 1975
- [j2]Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita:
Easily Testable Sequential Machines with Extra Inputs. IEEE Trans. Computers 24(8): 821-826 (1975) - 1974
- [j1]Hideo Fujiwara, Kozo Kinoshita:
Design of Diagnosable Sequential Machines Utilizing Extra Outputs. IEEE Trans. Computers 23(2): 138-145 (1974)
Conference and Workshop Papers
- 2019
- [c157]Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method Based on k-Cycle Testing for Finite State Machines. IOLTS 2019: 232-235 - 2016
- [c156]Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A scheduling method for hierarchical testability based on test environment generation results. ETS 2016: 1-2 - [c155]Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara:
A unified test and fault-tolerant multicast solution for network-on-chip designs. ITC 2016: 1-9 - 2015
- [c154]Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. ATS 2015: 37-42 - 2013
- [c153]Dong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-aware test scheduling for NOC-based 3D integrated circuits. VLSI-SoC 2013: 96-101 - 2011
- [c152]Hideo Fujiwara, Katsuya Fujiwara, Hideo Tamamoto:
Secure scan design using shift register equivalents against differential behavior attack. ASP-DAC 2011: 818-823 - [c151]Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara:
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS 2011: 147-152 - [c150]Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. ETS 2011: 203 - [c149]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Temperature-Variation-Aware Test Pattern Optimization. ETS 2011: 214 - [c148]Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara:
Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9 - 2010
- [c147]Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara:
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS 2010: 264-267 - [c146]Hideo Fujiwara, Marie Engelene J. Obien:
Secure and testable scan design using extended de Bruijn graphs. ASP-DAC 2010: 413-418 - [c145]Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium 2010: 206-211 - [c144]Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara:
Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318 - [c143]Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara:
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium 2010: 371-374 - [c142]Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto:
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. DDECS 2010: 193-196 - [c141]Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara:
A synthesis method to propagate false path information from RTL to gate level. DDECS 2010: 197-200 - [c140]Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara:
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA 2010: 20-25 - [c139]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. ETS 2010: 259 - [c138]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara:
Test pattern selection to optimize delay test quality with a limited size of test set. ETS 2010: 260 - [c137]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78 - [c136]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26 - [c135]Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara:
Constrained ATPG for functional RTL circuits using F-Scan. ITC 2010: 615-624 - [c134]Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara:
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. ITC 2010: 625-634 - [c133]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh:
On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398 - [c132]Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193 - 2009
- [c131]Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC 2009: 660-665 - [c130]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC 2009: 793-798 - [c129]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Partial Scan Approach for Secret Information Protection. ETS 2009: 143-148 - [c128]Hongxia Fang, Krishnendu Chakrabarty, Hideo Fujiwara:
RTL DFT techniques to enhance defect coverage for functional test sequences. HLDVT 2009: 160-165 - [c127]Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS 2009: 71-76 - [c126]Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara:
Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC 2009: 172-173 - 2008
- [c125]Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara:
Localized random access scan: Towards low area and routing overhead. ASP-DAC 2008: 565-570 - [c124]Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko:
Untestable Fault Identification in Sequential Circuits Using Model-Checking. ATS 2008: 21-26 - [c123]Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. ATS 2008: 27-34 - [c122]Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS 2008: 125-130 - [c121]Tomokazu Yoneda, Hideo Fujiwara:
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE 2008: 1366-1369 - 2007
- [c120]Dan Zhao, Unni Chandran, Hideo Fujiwara:
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. ASP-DAC 2007: 714-719 - [c119]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725 - [c118]Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara:
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. ATS 2007: 65-68 - [c117]Dan Zhao, Ronghua Huang, Hideo Fujiwara:
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE. ATS 2007: 107-110 - [c116]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS 2007: 187-192 - [c115]Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara:
Test Scheduling for Memory Cores with Built-In Self-Repair. ATS 2007: 199-206 - [c114]Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara:
Fault-dependent/independent Test Generation Methods for State Observable FSMs. ATS 2007: 275-280 - [c113]Dong Xiang, Krishnendu Chakrabarty, Dianwei Hu, Hideo Fujiwara:
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. ATS 2007: 329-334 - [c112]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. ATS 2007: 459-462 - [c111]Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687 - [c110]Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara:
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE 2007: 231-236 - [c109]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS 2007: 35-42 - [c108]Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423 - [c107]Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara:
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS 2007: 2942-2945 - [c106]Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara:
Fast and effective fault simulation for path delay faults based on selected testable paths. ITC 2007: 1-10 - [c105]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS 2007: 369-374 - [c104]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test. VTS 2007: 381-388 - 2006
- [c103]Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara:
A memory grouping method for sharing memory BIST logic. ASP-DAC 2006: 671-676 - [c102]Chia Yee Ooi, Hideo Fujiwara:
A New Scan Design Technique Based on Pre-Synthesis Thru Functions. ATS 2006: 163-168 - [c101]Hideo Fujiwara, Jiaguang Sun, Krishnendu Chakrabarty, Yang Zhao, Dong Xiang:
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture. ATS 2006: 299-306 - [c100]Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Design for Testability of Software-Based Self-Test for Processors. ATS 2006: 375-380 - [c99]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. ATS 2006: 409-414 - [c98]Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
Power-constrained test scheduling for multi-clock domain SoCs. DATE 2006: 297-302 - [c97]Ilia Polian, Hideo Fujiwara:
Functional constraints vs. test compression in scan-based delay testing. DATE 2006: 1039-1044 - [c96]Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell:
Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189 - [c95]Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara:
Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT 2006: 274-279 - [c94]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006: 230-236 - [c93]Chia Yee Ooi, Hideo Fujiwara:
A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD 2006: 425-431 - [c92]Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun:
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. ICCD 2006: 446-451 - [c91]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. VLSI-SoC (Selected Papers) 2006: 301-316 - [c90]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC 2006: 308-313 - [c89]Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
BIST Pretest of ICs: Risks and Benefits. VTS 2006: 142-149 - 2005
- [c88]Dong Xiang, Ming-Jing Chen, Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. Asian Test Symposium 2005: 126-131 - [c87]Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara:
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. Asian Test Symposium 2005: 150-155 - [c86]Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium 2005: 254-259 - [c85]Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic. Asian Test Symposium 2005: 260-265 - [c84]Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium 2005: 288-293 - [c83]Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311 - [c82]Dong Xiang, Kaiwei Li, Hideo Fujiwara:
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. Asian Test Symposium 2005: 318-323 - [c81]Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki:
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium 2005: 444-449 - [c80]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. ETS 2005: 48-53 - [c79]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750 - [c78]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689 - [c77]Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara:
Design and analysis of multiple weight linear compactors of responses containing unknown values. ITC 2005: 10 - 2004
- [c76]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39 - [c75]Kazuko Kambe, Michiko Inoue, Hideo Fujiwara:
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. Asian Test Symposium 2004: 152-157 - [c74]Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara:
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Asian Test Symposium 2004: 342-347 - [c73]Chia Yee Ooi, Hideo Fujiwara:
Classification of Sequential Circuits Based on ?k Notation. Asian Test Symposium 2004: 348-353 - [c72]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A design methodology to realize delay testable controllers using state transition information. ETS 2004: 168-173 - [c71]Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard:
An efficient scan tree design for test time reduction. ETS 2004: 174-179 - [c70]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933- - 2003
- [c69]Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara:
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. Asian Test Symposium 2003: 12-17 - [c68]Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium 2003: 58-63 - [c67]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71 - [c66]Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara:
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135 - [c65]Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara:
Test Synthesis for Datapaths Using Datapath-Controller Functions. Asian Test Symposium 2003: 294-299 - [c64]Dong Xiang, Shan Gu, Hideo Fujiwara:
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. Asian Test Symposium 2003: 300-305 - [c63]Erik Larsson, Hideo Fujiwara:
Optimal System-on-Chip Test Scheduling. Asian Test Symposium 2003: 306-311 - [c62]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417 - [c61]Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara:
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. DATE 2003: 10310-10315 - [c60]Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara:
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ITC 2003: 415-422 - [c59]Tomokazu Yoneda, Hideo Fujiwara:
Design for Consecutive Transparency of Cores in System-on-a-Chip. VTS 2003: 287-292 - [c58]Erik Larsson, Hideo Fujiwara:
Test Resource Partitioning and Optimization for SOC Designs. VTS 2003: 319-324 - 2002
- [c57]Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara:
Design for Two-Pattern Testability of Controller-Data Path Circuits. Asian Test Symposium 2002: 73-79 - [c56]Dong Xiang, Shan Gu, Hideo Fujiwara:
Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. Asian Test Symposium 2002: 86- - [c55]Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara:
A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design. Asian Test Symposium 2002: 128-133 - [c54]Emil Gizdarski, Hideo Fujiwara:
Fault Set Partition for Efficient Width Compression. Asian Test Symposium 2002: 194-199 - [c53]Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng:
Integrated Test Scheduling, Test Parallelization and TAMDesign. Asian Test Symposium 2002: 397-404 - [c52]Erik Larsson, Hideo Fujiwara:
Power constrained preemptive TAM scheduling. ETW 2002: 119-126 - [c51]Michiko Inoue, Chikateru Jinno, Hideo Fujiwara:
An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. ICCD 2002: 200-205 - [c50]Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa:
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. VTS 2002: 321-327 - 2001
- [c49]Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara:
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. ASP-DAC 2001: 331-334 - [c48]Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara:
Design for Hierarchical Two-Pattern Testability of Data Paths. Asian Test Symposium 2001: 11-16 - [c47]Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Asian Test Symposium 2001: 193-198 - [c46]Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara:
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. Asian Test Symposium 2001: 313-318 - [c45]Emil Gizdarski, Hideo Fujiwara:
A Framework for Low Complexity Static Learning. DAC 2001: 546-549 - [c44]Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara:
Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design 2001: 128-133 - [c43]Emil Gizdarski, Hideo Fujiwara:
SPIRIT: A Highly Robust Combinational Test Generation Algorithm. VTS 2001: 346-351 - [c42]Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara:
Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. DISC 2001: 123-135 - 2000
- [c41]Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara:
A non-scan DFT method at register-transfer level to achieve complete fault efficiency. ASP-DAC 2000: 599-604 - [c40]Emil Gizdarski, Hideo Fujiwara:
Spirit: satisfiability problem implementation for redundancy identification and test generation. Asian Test Symposium 2000: 171-178 - [c39]Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara:
Single-control testability of RTL data paths for BIST. Asian Test Symposium 2000: 210-215 - [c38]Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara:
Strong self-testability for data paths high-level synthesis. Asian Test Symposium 2000: 229-234 - [c37]Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403 - [c36]Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara:
Test Generation for Acyclic Sequential Circuits with Hold Registers. ICCAD 2000: 550-556 - [c35]Dong Xiang, Yi Xu, Hideo Fujiwara:
Non-scan design for testability for synchronous sequential circuits based on conflict analysis. ITC 2000: 520-529 - [c34]Hideo Fujiwara:
A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. VLSI Design 2000: 288-293 - [c33]Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara:
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. VLSI Design 2000: 300-305 - 1999
- [c32]Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium 1999: 5-12 - [c31]Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara:
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. Asian Test Symposium 1999: 192- - [c30]Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium 1999: 263-268 - [c29]Tomoya Takasaki, Hideo Fujiwara, Tomoo Inoue:
A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. Asian Test Symposium 1999: 309-314 - [c28]Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. ISPAN 1999: 394-399 - 1998
- [c27]Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara:
Partial Scan Design Methods Based on Internally Balanced Structure. ASP-DAC 1998: 211-216 - [c26]Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara:
A High-Level Synthesis Method for Weakly Testable Data Paths. Asian Test Symposium 1998: 40-45 - [c25]Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara:
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. Asian Test Symposium 1998: 190-197 - [c24]Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara:
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. Asian Test Symposium 1998: 204-211 - [c23]Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. GD 1998: 183-197 - [c22]Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
SelfStabilizing WaitFree Clock Synchronization with Bounded Space. OPODIS 1998: 129-144 - 1997
- [c21]Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara:
Non-scan design for testable data paths using thru operation. ASP-DAC 1997: 313-318 - [c20]Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Sequential Test Generation Based on Circuit Pseudo-Transformation. Asian Test Symposium 1997: 62-67 - [c19]Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara:
Testing for the programming circuit of LUT-based FPGAs. Asian Test Symposium 1997: 242-247 - [c18]Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara:
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs. Asian Test Symposium 1997: 276-281 - [c17]Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A Parallel Algorithm for Weighted Distance Transforms. IPPS 1997: 407-412 - [c16]Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara:
Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. WDAG 1997: 290-304 - [c15]Eiichiro Ueda, Yoshiaki Katayama, Toshimitsu Masuzawa, Hideo Fujiwara:
A latency-optimal superstabilizing mutual exclusion protocol. WSS 1997: 110-124 - 1996
- [c14]Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara:
A Test Methodology for Interconnect Structures of LUT-based FPGAs. Asian Test Symposium 1996: 68-74 - [c13]Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara:
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. Asian Test Symposium 1996: 130-135 - [c12]Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara:
A Snapshot Algorithm for Distributed Mobile Systems. ICDCS 1996: 734-743 - 1995
- [c11]Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto:
Universal test complexity of field-programmable gate arrays. Asian Test Symposium 1995: 259-265 - [c10]Tomoo Inoue, Hironori Maeda, Hideo Fujiwara:
A scheduling problem in test generation. VTS 1995: 344-349 - 1992
- [c9]Takayuki Fujino, Hideo Fujiwara:
An Efficient Test Generation Algorithm Based on Search State Dominance. FTCS 1992: 246-253 - [c8]Hideo Fujiwara, Akihiro Yamamoto:
Parity-Scan Design to Reduce the Cost of Test Application. ITC 1992: 283-292 - 1990
- [c7]Hideo Fujiwara:
Three-valued neural networks for test generation. FTCS 1990: 64-71 - 1989
- [c6]Hideo Fujiwara, Tomoo Inoue:
Optimal granularity of test generation in a distributed system. ICCAD 1989: 158-161 - 1988
- [c5]Hideo Fujiwara:
Computational complexity of controllability/observability problems for combinational circuits. FTCS 1988: 64-69 - [c4]Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone:
Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. ITC 1988: 642-648 - 1985
- [c3]Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita:
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. ITC 1985: 574-582 - 1983
- [c2]Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara:
Test generation for scan design circuits with tri-state modules and bidirectional terminals. DAC 1983: 71-78 - 1978
- [c1]Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita:
LORES - Logic Reorganization System. DAC 1978: 250-260
Coauthor Index
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