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ORCIDJaynarayan T. Tudu
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2020 – today
- 2024
[c23]Haripriya R. S, Soumitro Vyapari, Jaynarayan T. Tudu:
Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing. VLSID 2024: 712-717- 2022
- [c22]Anjum Riaz, Gaurav Kumar
, Jaynarayan T. Tudu, Satyadev Ahlawat:
On Protecting IJTAG from Data Sniffing and Alteration Attacks. ISVLSI 2022: 146-151 - [e1]Ambika Prasad Shah, Sudeb Dasgupta, Anand D. Darji, Jaynarayan T. Tudu:
VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers. Communications in Computer and Information Science 1687, Springer 2022, ISBN 978-3-031-21513-1 [contents] - [i1]Lakshmi Bhanuprakash Reddy Konduru, Vijaya Lakshmi, Jaynarayan T. Tudu:
Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption. CoRR abs/2212.12360 (2022) - 2021
- [j1]Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh:
A Framework for Configurable Joint-Scan Design-for-Test Architecture. J. Electron. Test. 37(5): 593-611 (2021) - 2020
- [c21]Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
LUT-based Circuit Approximation with Targeted Error Guarantees. ATS 2020: 1-6
2010 – 2019
- 2019
- [c20]Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh:
Preventing Scan Attack through Test Response Encryption. DFT 2019: 1-6 - [c19]Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
Securing Scan through Plain-text Restriction. IOLTS 2019: 251-252 - 2018
- [c18]Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
On Securing Scan Design Through Test Vector Encryption. ISCAS 2018: 1-5 - 2017
- [c17]Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh:
On Securing Scan Design from Scan-Based Side-Channel Attacks. ATS 2017: 58-63 - [c16]Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh:
Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS 2017: 132-137 - [c15]Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag:
A Cost Effective Technique for Diagnosis of Scan Chain Faults. VDAT 2017: 191-204 - 2016
- [c14]Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu:
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS 2016: 1-4 - [c13]Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh:
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS 2016: 233-238 - [c12]Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu:
Skip-scan: A methodology for test time reduction. VDAT 2016: 1-6 - [c11]Satyadev Ahlawat, Jaynarayan T. Tudu:
On minimization of test power through modified scan flip-flop. VDAT 2016: 1-6 - [c10]Rohini Gulve, Nihar Hage, Jaynarayan T. Tudu:
On determination of instantaneous peak and cycle peak switching using ILP. VDAT 2016: 1-6 - [c9]Jaynarayan T. Tudu:
JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power. VDAT 2016: 1-6 - [c8]Jaynarayan T. Tudu, Satyadev Ahlawat:
Guided shifting of test pattern to minimize test time in serial scan. VDAT 2016: 1-6 - 2015
- [c7]Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh:
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS 2015: 25-30 - 2013
- [c6]Jaynarayan T. Tudu, Deepak Malani, Virendra Singh:
Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. VDAT 2013: 345-352 - 2012
- [c5]Jaynarayan T. Tudu, Deepak Malani, Virendra Singh:
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. VDAT 2012: 172-179 - 2010
- [c4]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. ETS 2010: 259 - [c3]Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh:
On selection of state variables for delay test of identical functional units. EWDTS 2010: 200-203 - [c2]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78
2000 – 2009
- 2009
- [c1]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal:
On Minimization of Peak Power for Scan Circuit during Test. ETS 2009: 25-30
Coauthor Index
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