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ORCIDMichiaki Muraoka
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2010 – 2019
- 2014
[c18]Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga:
A critical net reshape-router for high-performance VLSI layout design. APCCAS 2014: 587-590- 2013
- [c17]Yoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga:
A multilayer crosstalk avoidance router using restricted maze grids. MWSCAS 2013: 641-644
2000 – 2009
- 2004
- [j1]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Trans. Inf. Syst. 87-D(3): 609-619 (2004) - [c16]Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada:
Design methodology for SoC arthitectures based on reusable virtual cores. ASP-DAC 2004: 256-262 - 2003
- [c15]Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida:
VCore-based design methodology. ASP-DAC 2003: 441-445 - [c14]Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada:
Synthesis for SoC architecture using VCores. ASP-DAC 2003: 446-452 - [c13]Yoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki:
VCore-based platform for SoC design. ASP-DAC 2003: 453-458 - [c12]Rafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka:
VCDS tool demonstration. ASP-DAC 2003: 459 - [c11]Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara:
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135 - [c10]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417 - 2002
- [c9]Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka:
A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium 2002: 55-60 - [c8]Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka:
A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium 2002: 305-310 - [c7]Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka:
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS 2002: 328-335
1990 – 1999
- 1997
- [c6]Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu:
A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium 1997: 306- - 1996
- [c5]Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka:
A Design for testability Method Using RTL Partitioning. Asian Test Symposium 1996: 88-93 - 1995
- [c4]Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka:
Design for testability using register-transfer level partial scan selection. ASP-DAC 1995 - 1993
- [c3]Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin:
A State Traversal Algorithm Using a State Covariance Matrix. DAC 1993: 97-101
1980 – 1989
- 1985
- [c2]Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa:
ACTAS: an accurate timing analysis system for VLSI. DAC 1985: 152-158 - 1982
- [c1]Kazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka:
Logic simulation for LSI. DAC 1982: 755-761
Coauthor Index
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