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ORCIDR. D. (Shawn) Blanton
R. D. Shawn Blanton – Ronald D. Blanton – Ronald Shawn Blanton – Ronald DeShawn Blanton
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2020 – today
- 2024
[c140]Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen:
Silent Data Corruption: Test or Reliability Problem? ETS 2024: 1-7- [c139]Chris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. Shawn Blanton:
Faulty Function Extraction for Defective Circuits. ETS 2024: 1-6 - [c138]Prabhu Vellaisamy, Harideep Nair, Di Wu, R. D. Shawn Blanton, John Paul Shen:
Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. ISVLSI 2024: 661-665 - [c137]Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen:
Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. VLSI-SoC 2024: 1-4 - [c136]Chris Nigh, Ronald D. Blanton:
Logic-AAA: Debug of Logic Failures with an on-ATE Expert System. VTS 2024: 1-6 - [i7]Harideep Nair
, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen:
OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. CoRR abs/2402.19376 (2024) - [i6]Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, R. D. (Shawn) Blanton, John Paul Shen:
tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. CoRR abs/2412.17955 (2024) - [i5]Prabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoyang Fan, Bin Qi, Jeff Chen, R. D. Shawn Blanton, John Paul Shen:
Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. CoRR abs/2412.19002 (2024) - 2023
- [j43]Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton:
Efficient Test Chip Design via Smart Computation. ACM Trans. Design Autom. Electr. Syst. 28(2): 22:1-22:31 (2023) - [c135]Wei Li, Fangzhou Wang, José M. F. Moura, R. D. (Shawn) Blanton:
Global Floorplanning via Semidefinite Programming. DAC 2023: 1-6 - [c134]Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen:
tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. ISVLSI 2023: 1-6 - [c133]Wei Li, Ruben Purdy, José M. F. Moura, R. D. Shawn Blanton:
Characterize the ability of GNNs in attacking logic locking. MLCAD 2023: 1-6 - 2022
- [c132]Ruben Purdy, Danielle Duvalsaint, R. D. Shawn Blanton:
Secuirty Metrics for Logic Circuits. HOST 2022: 53-56 - [c131]Ruben Purdy, R. D. Shawn Blanton:
Large-Scale Logic-Locking Attacks via Simulation. ISQED 2022: 1-6 - [c130]Wei Li, Chris Nigh, Danielle Duvalsaint, Subhasish Mitra, Ronald D. Blanton:
PEPR: Pseudo-Exhaustive Physically-Aware Region Testing. ITC 2022: 314-323 - 2021
- [j42]Samuel Pagliarini, Joseph Sweeney, Ken Mai, R. D. Shawn Blanton, Larry T. Pileggi, Subhasish Mitra:
Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test 38(4): 109-118 (2021) - [c129]Danielle Duvalsaint, R. D. Shawn Blanton:
Characterizing Corruptibility of Logic Locks using ATPG. ITC 2021: 213-222 - [c128]Chris Nigh, Gaurav Bhargava, Ronald D. Blanton:
AAA: Automated, On-ATE AI Debug of Scan Chain Failures. ITC 2021: 314-318 - [c127]Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton:
Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis. VTS 2021: 1-7 - 2020
- [j41]Joseph Sweeney, Ruben Purdy, Ronald D. Blanton, Lawrence T. Pileggi:
CircuitGraph: A Python package for Boolean circuits. J. Open Source Softw. 5(55): 2646 (2020) - [j40]Cuong Manh Nguyen, Xin Li, Ronald DeShawn Blanton, Xiang Li:
Partial Bayesian Co-training for Virtual Metrology. IEEE Trans. Ind. Informatics 16(5): 2937-2945 (2020) - [j39]Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. (Shawn) Blanton:
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. ACM Trans. Design Autom. Electr. Syst. 25(5): 43:1-43:20 (2020) - [c126]Jianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrión Schäfer:
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. DAC 2020: 1-6 - [c125]Cuong Nguyen, Xin Li, R. D. Shawn Blanton, Xiang Li:
Efficient Classification via Partial Co-Training for Virtual Metrology. ETFA 2020: 753-760 - [c124]Farimah Farahmandi, Ozgur Sinanoglu, Ronald D. Blanton, Samuel Pagliarini:
Design Obfuscation versus Test. ETS 2020: 1-10 - [c123]Zeye Liu, R. D. Shawn Blanton:
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. ITC 2020: 1-10 - [c122]Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution. ITC 2020: 1-10 - [c121]Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
Knowledge Transfer for Diagnosis Outcome Preview with Limited Data. ITC 2020: 1-9 - [c120]Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton:
Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors. ITC-Asia 2020: 59-64 - [c119]Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest. ITC-Asia 2020: 65-70 - [c118]Ayush Jain, Ujjwal Guin, M. Tanjidur Rahman, Navid Asadizanjani, Danielle Duvalsaint, R. D. Shawn Blanton:
Special Session: Novel Attacks on Logic-Locking. VTS 2020: 1-10 - [c117]Soumya Mittal, R. D. Shawn Blanton:
A Deterministic-Statistical Multiple-Defect Diagnosis Methodology. VTS 2020: 1-6 - [i4]Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks:
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020)
2010 – 2019
- 2019
- [j38]Xuanle Ren, Francisco Pimentel Torres, Ronald D. Blanton, Vítor Grade Tavares:
IC Protection Against JTAG-Based Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 149-162 (2019) - [j37]Matthew Layne Beckler, Ronald D. Blanton:
On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 322-334 (2019) - [c116]Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton:
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. DAC 2019: 200 - [c115]Soumya Mittal, R. D. Shawn Blanton:
LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology. ETS 2019: 1-6 - [c114]Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton:
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. ICCD 2019: 11-19 - [c113]Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton:
Characterization of Locked Combinational Circuits via ATPG. ITC 2019: 1-10 - [c112]Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton:
Improving Test Chip Design Efficiency via Machine Learning. ITC 2019: 1-10 - [c111]Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton:
Characterization of Locked Sequential Circuits via ATPG. ITC-Asia 2019: 97-102 - [c110]Chenlei Fang, Qicheng Huang, Soumya Mittal, R. D. Shawn Blanton:
Diagnosis Outcome Preview through Learning. VTS 2019: 1-6 - [c109]Ben Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton:
Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle. VTS 2019: 1-6 - [i3]Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, Ronald D. Blanton:
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. CoRR abs/1904.02835 (2019) - 2018
- [j36]Yang Xue, Xin Li, Ronald D. Blanton:
Improving Diagnostic Resolution of Failing ICs Through Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1288-1297 (2018) - [j35]Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu:
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. ACM Trans. Reconfigurable Technol. Syst. 11(3): 17:1-17:24 (2018) - [c108]Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu:
Quantized deep neural networks for energy efficient hardware-based inference. ASP-DAC 2018: 1-8 - [c107]Abhinav Goel, Zeye Liu, Ronald D. Blanton:
CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation. IEEE BigData 2018: 4723-4729 - [c106]Xuanle Ren, R. D. (Shawn) Blanton, Vítor Grade Tavares:
Detection of IJTAG attacks using LDPC-based feature reduction and machine learning. ETS 2018: 1-6 - [c105]Zeye Liu, Ronald D. Blanton:
Back-End Layout Reflection for Test Chip Design. ICCD 2018: 456-463 - [c104]Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. Shawn Blanton:
Improving Diagnosis Efficiency via Machine Learning. ITC 2018: 1-10 - [c103]Soumya Mittal, R. D. (Shawn) Blanton:
NOIDA: Noise-resistant Intra-cell Diagnosis. VTS 2018: 1-6 - [i2]Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton:
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. CoRR abs/1802.02178 (2018) - 2017
- [j34]Ronald Shawn Blanton, Fa Wang, Cheng Xue, Pranab K. Nag, Yang Xue, Xin Li:
DFM Evaluation Using IC Diagnosis Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 463-474 (2017) - [c102]Soumya Mittal, R. D. (Shawn) Blanton:
PADLOC: Physically-Aware Defect Localization and Characterization. ATS 2017: 212-218 - [c101]Cuong Nguyen, Xin Li, Ronald Shawn Blanton, Xiang Li:
Partial co-training for virtual metrology. ETFA 2017: 1-8 - [c100]Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton:
Multiple-defect diagnosis for Logic Characterization Vehicles. ETS 2017: 1-6 - [c99]Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton:
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. ACM Great Lakes Symposium on VLSI 2017: 35-40 - [c98]Xiang Lin, R. D. (Shawn) Blanton, Donald E. Thomas:
Random Forest Architectures on FPGA for Multiple Applications. ACM Great Lakes Symposium on VLSI 2017: 415-418 - [c97]Matthew Beckler, Ronald D. Blanton:
Fault simulation acceleration for TRAX dictionary construction using GPUs. ITC 2017: 1-9 - [c96]Zeye Liu, Phillip Fynan, Ronald D. Blanton:
Front-end layout reflection for test chip design. ITC 2017: 1-10 - [c95]Matthew Beckler, R. D. Shawn Blanton:
GPU-accelerated fault dictionary generation for the TRAX fault model. ITC-Asia 2017: 34-39 - [c94]Cheng Xue, R. D. (Shawn) Blanton:
Test-set reordering for improving diagnosability. VTS 2017: 1-6 - 2016
- [j33]R. D. Shawn Blanton, David Yeh:
Test: Wisdom From the Giants, Visions for the Future - Part 2. IEEE Des. Test 33(1): 77-84 (2016) - [j32]Hongfei Wang, R. D. (Shawn) Blanton:
Ensemble Reduction via Logic Minimization. ACM Trans. Design Autom. Electr. Syst. 21(4): 67:1-67:17 (2016) - [c93]Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton:
Achieving 100% cell-aware coverage by design. DATE 2016: 109-114 - [c92]Xuanle Ren, Ronald D. Blanton, Vítor Grade Tavares:
A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks. ISVLSI 2016: 541-546 - [c91]Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton:
Logic characterization vehicle design reflection via layout rewiring. ITC 2016: 1-10 - [c90]Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen:
Diagnostic resolution improvement through learning-guided physical failure analysis. ITC 2016: 1-10 - [c89]Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton:
Test chip design for optimal cell-aware diagnosability. ITC 2016: 1-8 - 2015
- [j31]Wing Chiu Jason Tam, Ronald Shawn Blanton:
LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(8): 1278-1290 (2015) - [c88]Xuanle Ren, Vítor Grade Tavares, R. D. (Shawn) Blanton:
Detection of illegitimate access to JTAG via statistical learning in chip. DATE 2015: 109-114 - [c87]Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas:
Statistical Learning in Chip (SLIC). ICCAD 2015: 664-669 - [c86]Cheng Xue, R. D. (Shawn) Blanton:
A one-pass test-selection method for maximizing test coverage. ICCD 2015: 621-628 - [c85]R. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye (Dexter) Liu:
Design reflection for optimal test-chip implementation. ITC 2015: 1-10 - [c84]Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter:
Special session: Hot topics: Statistical test methods. VTS 2015: 1-2 - [c83]Ben Niewenhuis, Ronald D. Blanton:
Efficient built-in self test of regular logic characterization vehicles. VTS 2015: 1-6 - [c82]Xuanle Ren, Mitchell Martin, Ronald D. Blanton:
Improving accuracy of on-chip diagnosis via incremental learning. VTS 2015: 1-6 - 2014
- [j30]Wing Chiu Tam, R. D. (Shawn) Blanton:
Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1559-1572 (2014) - [j29]Sounil Biswas, Hongfei Wang, R. D. (Shawn) Blanton:
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis. ACM Trans. Design Autom. Electr. Syst. 19(2): 20:1-20:23 (2014) - [c81]Cheng Xue, R. D. (Shawn) Blanton:
Predicting IC Defect Level Using Diagnosis. ATS 2014: 113-118 - [c80]John A. Porche, R. D. (Shawn) Blanton:
Physically-Aware Diagnostic Resolution. ATS 2014: 206-211 - [c79]Xin Li, Ronald Shawn Blanton, Pulkit Grover, Donald E. Thomas:
Ultra-low-power biomedical circuit design and optimization: Catching the don't cares. ISIC 2014: 115-118 - [c78]Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas:
SLIC: Statistical learning in chip. ISIC 2014: 119-123 - [c77]Ronald D. Blanton, Ben Niewenhuis, Carl Taylor:
Logic characterization vehicle design for maximal information extraction for yield learning. ITC 2014: 1-10 - [c76]Shanghang Zhang, Xin Li, Ronald D. Blanton, José Machado da Silva, John M. Carulli Jr., Kenneth M. Butler:
Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling. ITC 2014: 1-10 - 2013
- [c75]Ronald D. Blanton, Fa Wang, Cheng Xue, Pranab K. Nag, Yang Xue, Xin Li:
DREAMS: DFM rule EvAluation using manufactured silicon. ICCAD 2013: 99-106 - [c74]Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai:
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC 2013: 1-8 - [c73]Yang Xue, Osei Poku, Xin Li, Ronald D. Blanton:
PADRE: Physically-Aware Diagnostic Resolution Enhancement. ITC 2013: 1-10 - [c72]Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia:
Special session 4B: Elevator talks. VTS 2013: 1 - 2012
- [j28]R. D. (Shawn) Blanton, Wing Chiu Tam, Xiaochun Yu, Jeffrey E. Nelson, Osei Poku:
Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations. IEEE Des. Test Comput. 29(1): 36-47 (2012) - [j27]Wing Chiu Tam, Ronald D. Blanton:
Physically-Aware Analysis of Systematic Defects in Integrated Circuits. IEEE Des. Test Comput. 29(5): 81-93 (2012) - [j26]Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar:
Physically-Aware N-Detect Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 308-321 (2012) - [j25]Wing Chiu Tam, R. D. (Shawn) Blanton:
SLIDER: Simulation of Layout-Injected Defects for Electrical Responses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 918-929 (2012) - [j24]Xiaochun Yu, R. D. (Shawn) Blanton:
Diagnosis-Assisted Adaptive Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1405-1416 (2012) - [j23]Xiaochun Yu, Ronald D. Blanton:
Improving Diagnosis Through Failing Behavior Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1614-1625 (2012) - [c71]Hongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, Ronald D. Blanton:
Test-data volume optimization for diagnosis. DAC 2012: 567-572 - [c70]Matthew Beckler, R. D. (Shawn) Blanton:
On-chip diagnosis for early-life and wear-out failures. ITC 2012: 1-10 - 2011
- [j22]Sounil Biswas, Ronald D. Blanton:
Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 148-158 (2011) - [j21]Yen-Tzu Lin, R. D. (Shawn) Blanton:
METER: Measuring Test Effectiveness Regionally. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1058-1071 (2011) - [j20]Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton:
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1814-1827 (2011) - [c69]Wing Chiu Tam, R. D. (Shawn) Blanton:
To DFM or not to DFM? DAC 2011: 65-70 - [c68]Xiaochun Yu, R. D. (Shawn) Blanton:
Statistical defect-detection analysis of test sets using readily-available tester data. ICCAD 2011: 768-773 - [c67]Wing Chiu Tam, R. D. (Shawn) Blanton:
Physically-aware analysis of systematic defects in integrated circuits. ITC 2011: 1-10 - [c66]Wing Chiu Tam, Ronald D. Blanton:
SLIDER: A fast and accurate defect simulation framework. VTS 2011: 172-177 - [e1]Bill Eklow, R. D. (Shawn) Blanton:
2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-0153-5 [contents] - 2010
- [j19]David S. Ricketts, James A. Bain, Yi Luo, Ronald D. Blanton, Kenneth Mai, Gary K. Fedder:
Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems. Proc. IEEE 98(12): 2061-2075 (2010) - [j18]Xiaochun Yu, Ronald D. Blanton:
Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 977-987 (2010) - [c65]Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton:
Automatic classification of bridge defects. ITC 2010: 305-314 - [c64]Wing Chiu Tam, Osei Poku, Ronald D. Blanton:
Systematic defect identification through layout snippet clustering. ITC 2010: 378-387 - [c63]Xiaochun Yu, Ronald D. Blanton:
Estimating defect-type distributions through volume diagnosis and defect behavior attribution. ITC 2010: 664-673 - [c62]Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly:
Evaluating yield and testing impact of sub-wavelength lithography. VTS 2010: 200-205
2000 – 2009
- 2009
- [c61]Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton:
Automated failure population creation for validating integrated circuit diagnosis methods. DAC 2009: 708-713 - [c60]Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton:
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. ICCAD 2009: 433-440 - [c59]Yen-Tzu Lin, Ronald D. Blanton:
Test effectiveness evaluation through analysis of readily-available tester data. ITC 2009: 1-10 - [c58]Xiaochun Yu, Yen-Tzu Lin, Wing Chiu Tam, Osei Poku, Ronald D. Blanton:
Controlling DPPM through Volume Diagnosis. VTS 2009: 134-139 - [c57]Yen-Tzu Lin, Chukwuemeka U. Ezekwe, Ronald D. Blanton:
Physically-Aware N-Detect Test Relaxation. VTS 2009: 197-202 - [c56]Sounil Biswas, Ronald D. Blanton:
Maintaining Accuracy of Test Compaction through Adaptive Re-learning. VTS 2009: 257-263 - 2008
- [c55]Xiaochun Yu, R. D. (Shawn) Blanton:
Multiple defect diagnosis using no assumptions on failing pattern characteristics. DAC 2008: 361-366 - [c54]Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton:
Precise failure localization using automated layout analysis of diagnosis candidates. DAC 2008: 367-372 - [c53]Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi:
Automated Testability Enhancements for Logic Brick Libraries. DATE 2008: 480-485 - [c52]Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton:
Physically-Aware N-Detect Test Pattern Selection. DATE 2008: 634-639 - [c51]Jason G. Brown, R. D. (Shawn) Blanton:
Automated Standard Cell Library Analysis for Improved Defect Modeling. ISQED 2008: 643-648 - [c50]Sounil Biswas, Ronald D. Blanton:
Improving the Accuracy of Test Compaction through Adaptive Test Update. ITC 2008: 1 - [c49]Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar:
Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. ITC 2008: 1-9 - [c48]Xiaochun Yu, Ronald D. Blanton:
An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis. ITC 2008: 1-9 - [c47]Sounil Biswas, R. D. (Shawn) Blanton:
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. VTS 2008: 299-308 - 2007
- [j17]Jason G. Brown, R. D. (Shawn) Blanton:
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. J. Electron. Test. 23(2-3): 131-144 (2007) - [c46]Osei Poku, Ronald D. Blanton:
Delay defect diagnosis using segment network faults. ITC 2007: 1-10 - [i1]Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi:
Specification Test Compaction for Analog Circuits and MEMS. CoRR abs/0710.4719 (2007) - 2006
- [j16]Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer:
Extracting Defect Density and Size Distributions from Product ICs. IEEE Des. Test Comput. 23(5): 390-400 (2006) - [j15]Sounil Biswas, Ronald D. Blanton:
Statistical Test Compaction Using Binary Decision Trees. IEEE Des. Test Comput. 23(6): 452-462 (2006) - [j14]Tao Jiang, R. D. (Shawn) Blanton:
Inductive fault analysis of surface-micromachined MEMS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1104-1116 (2006) - [j13]Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni:
Defect Modeling Using Fault Tuples. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2450-2464 (2006) - [c45]Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton:
Multiple-detect ATPG based on physical neighborhoods. DAC 2006: 1099-1102 - [c44]Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton:
Extraction of defect density and size distributions from wafer sort test results. DATE 2006: 913-918 - [c43]Naresh K. Bhatti, Ronald D. Blanton:
Diagnostic Test Generation for Arbitrary Faults. ITC 2006: 1-9 - [c42]Rao Desineni, Osei Poku, Ronald D. Blanton:
A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. ITC 2006: 1-10 - [c41]Jason G. Brown, R. D. (Shawn) Blanton:
Exploiting Regularity for Inductive Fault Analysis. VTS 2006: 364-369 - 2005
- [c40]Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi:
Specification Test Compaction for Analog Circuits and MEMS. DATE 2005: 164-169 - [c39]R. D. (Shawn) Blanton, Subhasish Mitra:
Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. VLSI Design 2005: 8-9 - [c38]Rao Desineni, R. D. (Shawn) Blanton:
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. VTS 2005: 366-373 - 2004
- [c37]Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton:
Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. ISVLSI 2004: 173-178 - [c36]Jason G. Brown, R. D. (Shawn) Blanton:
CAEN-BIST: Testing the NanoFabric. ITC 2004: 462-471 - [c35]Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC 2004: 508-517 - [c34]Nilmoni Deb, R. D. (Shawn) Blanton:
Multi-Modal Built-In Self-Test for Symmetric Microsystems. VTS 2004: 139-147 - [c33]Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton:
Generalized Sensitization using Fault Tuples. VTS 2004: 297-303 - 2003
- [j12]Ronald D. Blanton, John P. Hayes:
On the properties of the input pattern fault model. ACM Trans. Design Autom. Electr. Syst. 8(1): 108-124 (2003) - [c32]Rahul Kundu, R. D. (Shawn) Blanton:
ATPG for Noise-Induced Switch Failures in Domino Logic. ICCAD 2003: 765-769 - [c31]Rahul Kundu, R. D. (Shawn) Blanton:
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. ITC 2003: 122-130 - [c30]Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton:
Progressive Bridge Identification. ITC 2003: 309-318 - [c29]Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey:
Deformations of IC Structure in Test and Yield Learning. ITC 2003: 856-865 - [c28]R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah:
Analyzing the Effectiveness of Multiple-Detect Test Sets. ITC 2003: 876-885 - 2002
- [j11]Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly:
Modeling the Economics of Testing: A DFT Perspective. IEEE Des. Test Comput. 19(1): 29-41 (2002) - [j10]Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton:
Test vector generation for charge sharing failures in dynamic logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1502-1508 (2002) - [j9]Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi:
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. VLSI Design 15(3): 605-618 (2002) - [c27]Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels:
Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC 2002: 233-241 - [c26]Nilmoni Deb, R. D. (Shawn) Blanton:
Built-In Self Test of CMOS-MEMS Accelerometers. ITC 2002: 1075-1084 - [c25]Kumar N. Dwarakanath, R. D. (Shawn) Blanton:
Exploiting Dominance and Equivalence using Fault Tuples. VTS 2002: 269-274 - [c24]Rahul Kundu, R. D. (Shawn) Blanton:
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. VTS 2002: 379-388 - [c23]Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim:
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS 2002: 449-450 - 2001
- [c22]Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi:
False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731 - [c21]Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen:
Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. HLDVT 2001: 3-8 - [c20]Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman:
Designing and Implementing Efficient BISR Techniques for Embedded RAMs. LATW 2001: 248-252 - [c19]Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton:
Testing of Dynamic Logic Circuits Based on Charge Sharing. VTS 2001: 396-403 - 2000
- [j8]Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
Effectiveness of Microarchitecture Test Program Generation. IEEE Des. Test Comput. 17(4): 38-49 (2000) - [j7]Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
A Buffer-Oriented Methodology for Microarchitecture Validation. J. Electron. Test. 16(1-2): 49-65 (2000) - [j6]Ronald D. Blanton, John P. Hayes:
On the design of fast, easily testable ALU's. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 220-223 (2000) - [c18]Kumar N. Dwarakanath, Ronald D. Blanton:
Universal fault simulation using fault tuples. DAC 2000: 786-789 - [c17]Rahul Kundu, Ronald D. Blanton:
Identification of crosstalk switch failures in domino CMOS circuits. ITC 2000: 502-509 - [c16]Nilmoni Deb, Ronald D. Blanton:
Analysis of failure sources in surface-micromachined MEMS. ITC 2000: 739-749 - [c15]Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton:
Universal test generation using fault tuples. ITC 2000: 812-819
1990 – 1999
- 1999
- [j5]Bernard Courtois, R. D. (Shawn) Blanton:
Guest Editors' Introduction. IEEE Des. Test Comput. 16(4): 16-17 (1999) - [j4]Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton:
Hierarchical Design and Test of Integrated Microsystems. IEEE Des. Test Comput. 16(4): 18-27 (1999) - [j3]Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R. D. (Shawn) Blanton, John Paul Shen:
An integrated functional performance simulator. IEEE Micro 19(3): 26-35 (1999) - [c14]Tao Jiang, Ronald D. Blanton:
Particulate failures for surface-micromachined MEMS. ITC 1999: 329-337 - [c13]R. D. (Shawn) Blanton:
IDDQ-Testability of Tree Circuits. VLSI Design 1999: 78-86 - [c12]Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
Superscalar Processor Validation at the Microarchitecture Level. VLSI Design 1999: 300-305 - 1998
- [c11]William E. Dougherty, R. D. (Shawn) Blanton:
Using regression analysis for GA-based ATPG parameter optimization. ICCD 1998: 516-521 - [c10]Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla:
Failure modes for stiction in surface-micromachined MEMS. ITC 1998: 551-556 - [c9]Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton:
MEMS fault model generation using CARAMEL. ITC 1998: 557-566 - [c8]Jean-Michel Karam, Marcelo Lubaszewski, R. D. Shawn Blanton, Andrew Richardson:
Testing MEMS. VTS 1998: 320-321 - 1997
- [j2]R. D. (Shawn) Blanton, John P. Hayes:
Testability Properties of Divergent Trees. J. Electron. Test. 11(3): 197-209 (1997) - [c7]Ronald D. Blanton, John P. Hayes:
The input pattern fault model and its application. ED&TC 1997: 628 - [c6]Ronald D. Blanton, John P. Hayes:
Properties of the Input Pattern Fault Model. ICCD 1997: 372-380 - [c5]Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly:
To DFT or Not to DFT? ITC 1997: 557-566 - [c4]Abhijeet Kolpekwar, Ronald D. Blanton:
Development of a MEMS Testing Methodology. ITC 1997: 923-931 - 1996
- [j1]Ronald D. Blanton, John P. Hayes:
Testability of Convergent Tree Circuits. IEEE Trans. Computers 45(8): 950-963 (1996) - [c3]Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani:
Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC 1996: 757-766 - [c2]R. D. (Shawn) Blanton, John P. Hayes:
Design of a fast, easily testable ALU. VTS 1996: 9-16 - 1995
- [b1]R. D. (Shawn) Blanton:
Design and testing of regular circuits. University of Michigan, USA, 1995 - 1993
- [c1]Ronald D. Blanton, John P. Hayes:
Efficient Testing of Tree Circuits. FTCS 1993: 176-185
Coauthor Index
Zeye Liu 0001
aka: Zeye (Dexter) Liu
aka: Zeye (Dexter) Liu
Ben Niewenhuis
aka: Benjamin Niewenhuis
aka: Benjamin Niewenhuis
Wing Chiu Tam
aka: Wing Chiu Jason Tam
aka: Wing Chiu Jason Tam
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