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ORCIDTaewhan Kim 0001
Person information
- affiliation: Seoul National University, Department of Electrical and Computer Engineering, Seoul, Korea
- affiliation: KAIST, Advanced Information Technology Research Center, Korea
- affiliation (PhD 1993): University of Illinois at Urbana-Champaign, School of computer science, Champaign, IL, USA
Other persons with the same name
- Taewhan Kim — disambiguation page
- Taewhan Kim 0002
![[0000-0002-2126-0704]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-2126-0704")
— Yonsei University, Seoul, Korea
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Journal Articles
- 2024
[j64]Taewhan Kim:
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024). IEEE Des. Test 41(3): 63-64 (2024)- [j63]Jooyeon Jeong, Taewhan Kim:
Placement legalization for heterogeneous cells of non-integer multiple-heights. Integr. 97: 102177 (2024) - [j62]Kyungjoon Chang, Taewhan Kim:
Pre-route timing prediction and optimization with graph neural network models. Integr. 99: 102262 (2024) - [j61]Kyeonghyeon Baek, Taewhan Kim:
CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 627-640 (2024) - [j60]Soomin Kim, Taewhan Kim:
Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1538-1551 (2024) - [j59]Jaehoon Ahn, Kyungjoon Chang, Kyumyung Choi, Taewhan Kim, Heechun Park:
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2493-2506 (2024) - [j58]Hyunbum Park, Kyeonghyeon Baek, Suwan Kim, Kyumyung Choi, Taewhan Kim:
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4786-4799 (2024) - 2023
- [j57]Eunsol Jeong, Taewhan Kim, Heechun Park:
Eliminating Minimum Implant Area Violations With Design Quality Preservation. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 611-621 (2023) - 2022
- [j56]Heechun Park, Taewhan Kim:
Speeding-up neuromorphic computation for neural networks: Structure optimization approach. Integr. 82: 104-114 (2022) - [j55]Sehyeon Chung, Taewhan Kim:
ECO routing based on network flow method. Integr. 86: 1-8 (2022) - [j54]Byungmin Ahn, Taewhan Kim:
Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 656-668 (2022) - [j53]Jeongwoo Heo, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyumyung Choi:
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1929-1942 (2022) - 2021
- [j52]Byungmin Ahn, Taewhan Kim:
Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks. J. Circuits Syst. Comput. 30(9): 2150158:1-2150158:19 (2021) - [j51]Gyoung-Hwan Hyun, Taewhan Kim:
Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 892-903 (2021) - [j50]Taehwan Kim, Heechun Park, Taewhan Kim:
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 499-511 (2021) - [j49]Jeongwoo Heo, Taewhan Kim:
Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1437-1450 (2021) - 2020
- [j48]Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyu-Myung Choi:
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. Integr. 74: 81-92 (2020) - 2019
- [j47]Heechun Park, Taewhan Kim:
Hybrid asynchronous circuit generation amenable to conventional EDA flow. Integr. 64: 29-39 (2019) - [j46]Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, Kyu-Myung Choi:
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1933-1946 (2019) - 2017
- [j45]Deokjin Joo, Taewhan Kim:
Clock buffer polarity assignment under useful skew constraints. Integr. 57: 52-61 (2017) - [j44]Juyeon Kim, Taewhan Kim:
Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 641-654 (2017) - 2016
- [j43]Juyeon Kim, Deokjin Joo, Taewhan Kim:
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. Integr. 52: 91-101 (2016) - [j42]Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2068-2081 (2016) - 2015
- [j41]Heechun Park, Taewhan Kim:
Synthesis of TSV Fault-Tolerant 3-D Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 266-279 (2015) - 2014
- [j40]Deokjin Joo, Taewhan Kim:
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 423-436 (2014) - [j39]Minseok Kang, Taewhan Kim:
Integrated Resource Allocation and Binding in Clock Mesh Synthesis. ACM Trans. Design Autom. Electr. Syst. 19(3): 30:1-30:28 (2014) - 2013
- [j38]Tak-Yung Kim, Taewhan Kim:
Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 138-151 (2013) - [j37]Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim:
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 392-405 (2013) - 2012
- [j36]Deokjin Joo, Minseok Kang, Taewhan Kim:
Design Methodologies for Reliable Clock Networks. J. Comput. Sci. Eng. 6(4): 257-266 (2012) - [j35]YongHwan Kim, Sanghoon Kwak, Taewhan Kim:
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. ACM Trans. Design Autom. Electr. Syst. 17(4): 43:1-43:29 (2012) - 2011
- [j34]Hochang Jang, Deokjin Joo, Taewhan Kim:
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 96-109 (2011) - [j33]Tak-Yung Kim, Taewhan Kim:
Clock Tree synthesis for TSV-based 3D IC designs. ACM Trans. Design Autom. Electr. Syst. 16(4): 48:1-48:21 (2011) - 2010
- [j32]Taewhan Kim:
Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results. J. Comput. Sci. Eng. 4(3): 189-206 (2010) - 2009
- [j31]Pilok Lim, Ki-Seok Chung, Taewhan Kim:
Thermal-Aware High-Level Synthesis Based on Network Flow Method. J. Circuits Syst. Comput. 18(5): 965-984 (2009) - [j30]Byunghyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim:
Thermal sensor allocation and placement for reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. 14(4): 50:1-50:23 (2009) - 2007
- [j29]Taewhan Kim, Jungeun Kim:
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 142-151 (2007) - 2006
- [j28]Yoonseo Choi, Taewhan Kim:
Memory Access Driven Storage Assignment for Variables in Embedded System Design. J. Circuits Syst. Comput. 15(2): 145-168 (2006) - [j27]Junhyung Um, Taewhan Kim:
Resource Sharing Combined with Layout Effects in High-Level Synthesis. J. VLSI Signal Process. 44(3): 231-243 (2006) - [j26]Young-Jun Kim, Taewhan Kim:
A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. J. VLSI Signal Process. 44(3): 269-283 (2006) - 2005
- [j25]Yoonseo Choi, Taewhan Kim, Hwansoo Han:
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 278-287 (2005) - 2004
- [j24]Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung:
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. IEEE Trans. Computers 53(7): 829-842 (2004) - [j23]Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 157-164 (2004) - [j22]Keoncheol Shin, Taewhan Kim:
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 766-775 (2004) - 2003
- [j21]Yoonseo Choi, Taewhan Kim:
Address assignment in DSP code generation - an integrated approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 976-984 (2003) - [j20]Junhyung Um, Taewhan Kim:
Synthesis of arithmetic circuits considering layout effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1487-1503 (2003) - [j19]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) - [j18]Chun-Gi Lyuh, Taewhan Kim:
High-level synthesis for low power based on network flow method. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 364-375 (2003) - [j17]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 879-887 (2003) - 2002
- [j16]Ki-Seok Chung, Taewhan Kim, C. L. Liu:
A Complete Model for Glitch Analysis in Logic Circuits. J. Circuits Syst. Comput. 11(2): 137-154 (2002) - [j15]Yoonseo Choi, Taewhan Kim:
Binding Algorithm for Power Optimization Based on Network Flow Method. J. Circuits Syst. Comput. 11(3): 259-272 (2002) - [j14]Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang:
Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 232-240 (2002) - [j13]Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu:
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) - [j12]Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu:
Synthesis and Optimization of Combinational Interface Circuits. J. VLSI Signal Process. 31(3): 243-261 (2002) - 2001
- [j11]Junhyung Um, Taewhan Kim:
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. IEEE Trans. Computers 50(3): 215-233 (2001) - [j10]Ki-Seok Chung, Taewhan Kim, C. L. Liu:
G-vector: A New Model for Glitch Analysis in Logic Circuits. J. VLSI Signal Process. 27(3): 235-251 (2001) - 2000
- [j9]Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung:
Decomposition of Bus-Invert Coding for Low-Power I/O. J. Circuits Syst. Comput. 10(1-2): 101-112 (2000) - [j8]Youngtae Kim, Taewhan Kim:
An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. J. Circuits Syst. Comput. 10(5-6): 279-292 (2000) - [j7]Taewhan Kim, Junhyung Um:
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 615-624 (2000) - [j6]Chaeryung Park, Taewhan Kim, C. L. Liu:
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. VLSI Design 11(4): 381-396 (2000) - 1998
- [j5]Taewhan Kim, William Jao, Steven W. K. Tjiang:
Circuit optimization using carry-save-adder cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 974-984 (1998) - [j4]Chaeryung Park, Taewhan Kim, C. L. Liu:
Register Allocation - A Hierarchical Reduction Approach. J. VLSI Signal Process. 19(3): 269-285 (1998) - 1996
- [j3]Taewhan Kim, C. L. Liu:
An integrated algorithm for incremental data path synthesis. J. VLSI Signal Process. 12(3): 265-285 (1996) - 1995
- [j2]Taewhan Kim, C. L. Liu:
A new approach to the multiport memory allocation problem in data path synthesis. Integr. 19(3): 133-160 (1995) - 1994
- [j1]Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu:
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 425-438 (1994)
Conference and Workshop Papers
- 2024
- [c100]Suwan Kim, Taewhan Kim:
Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology. DAC 2024: 126:1-126:6 - [c99]Jooyeon Jeong, Taewhan Kim:
Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. DAC 2024: 159:1-159:6 - [c98]Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim:
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. DATE 2024: 1-6 - [c97]Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim:
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. DATE 2024: 1-6 - [c96]Hwapyong Kim, Taewhan Kim:
Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing. ISCAS 2024: 1-5 - [c95]Suwan Kim, Hyunbum Park, Kyeonghyeon Baek, Kyumyung Choi, Taewhan Kim:
Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model. ISPD 2024: 103-111 - [c94]Taewhan Kim:
Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops. MWSCAS 2024: 33-36 - [c93]Yeongyeong Shin, Taewhan Kim:
Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design. SOCC 2024: 1-6 - [c92]Jayoung Yang, Taewhan Kim:
Improving Timing Quality Through Net Topology Optimization in Global Routing. SOCC 2024: 1-6 - 2023
- [c91]Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim:
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. DATE 2023: 1-6 - [c90]Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim:
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. DATE 2023: 1-6 - [c89]Hwapyong Kim, Taewhan Kim:
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. ACM Great Lakes Symposium on VLSI 2023: 321-326 - [c88]Suwan Kim, Taewhan Kim:
Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops. ICCAD 2023: 1-9 - [c87]Sora Park, Taewhan Kim:
Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating. ISCAS 2023: 1-5 - [c86]Doyeon Won, Soomin Kim, Taewhan Kim:
Machine Learning Driven Synthesis of Clock Gating. ISLPED 2023: 1-6 - [c85]Jinmyoung Kim, Taewhan Kim:
Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips. ISOCC 2023: 121-122 - [c84]Chaehyun Kim, Taewhan Kim:
Maximizing Power Saving Through State-Driven Clock Gating. ISOCC 2023: 123-124 - [c83]Kihwan Jeon, Taewhan Kim:
Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells. ISOCC 2023: 345-346 - [c82]Ilseon Ha, Taewhan Kim:
Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow. ISOCC 2023: 347-348 - [c81]Taewhan Kim:
Challenges on Design and Technology Co-Optimization: Design Automation Perspective. MWSCAS 2023: 212-216 - [c80]Jaewan Yang, Taewhan Kim:
Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling. SOCC 2023: 1-6 - 2022
- [c79]Suwan Kim, Taewhan Kim:
Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model. DATE 2022: 778-783 - [c78]Eunsol Jeong, Heechun Park, Taewhan Kim:
A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. DATE 2022: 933-938 - [c77]Soomin Kim, Taewhan Kim:
Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells. ICCAD 2022: 15:1-15:7 - [c76]Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim:
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. ICCAD 2022: 26:1-26:9 - [c75]Sora Park, Taewhan Kim:
Selective Clock Gating Based on Comprehensive Power Saving Analysis. ISCAS 2022: 230-231 - [c74]Doyeon Won, Taewhan Kim:
Improving Pin Accessibility of Standard Cells Through Fin Depopulation. ISCAS 2022: 2621-2622 - [c73]Soomin Kim, Taewhan Kim:
Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops. ISCAS 2022: 2623-2624 - [c72]Sehyeon Chung, Jooyeon Jeong, Taewhan Kim:
Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. ISLPED 2022: 17:1-17:6 - [c71]Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park:
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED 2022: 26:1-26:6 - [c70]Kyungjoon Chang, Taewhan Kim:
Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. ISOCC 2022: 119-120 - 2021
- [c69]Suwan Kim, Kyeongrok Jo, Taewhan Kim:
Boosting Pin Accessibility Through Cell Layout Topology Diversification. ASP-DAC 2021: 183-188 - [c68]Jongsung Kang, Taewhan Kim:
Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks. DATE 2021: 1526-1529 - [c67]Kyeonghyeon Baek, Taewhan Kim:
Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis. ICCAD 2021: 1-8 - [c66]Kyeongrok Jo, Taewhan Kim:
Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis. ICCD 2021: 517-524 - [c65]Jaejoon Yoon, Sehyeon Chung, Taewhan Kim:
Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. ISOCC 2021: 169-170 - [c64]Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim:
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. ISOCC 2021: 215-218 - [c63]Soomin Kim, Taewhan Kim:
Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits. ISQED 2021: 482-487 - [c62]Suwan Kim, Taewhan Kim:
Practical Approach to Cell Replacement for Resolving Pin Inaccessibility. MWSCAS 2021: 224-227 - [c61]Jooyeon Jeong, Taewhan Kim:
Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures. MWSCAS 2021: 228-231 - [c60]Eunsol Jeong, Heechun Park, Jooyeon Jeong, Taewhan Kim:
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. MWSCAS 2021: 232-235 - 2020
- [c59]Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. ASP-DAC 2020: 139-144 - [c58]Jeongwoo Heo, Taewhan Kim:
Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. ASP-DAC 2020: 587-592 - [c57]Taehwan Kim, Gyoung-Hwan Hyun, Taewhan Kim:
Steady state driven power gating for lightening always-on state retention storage. ISLPED 2020: 79-84 - 2019
- [c56]Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. ISVLSI 2019: 146-151 - 2018
- [c55]Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi:
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. ASP-DAC 2018: 500-506 - [c54]Heechun Park, Taewhan Kim:
Structure optimizations of neuromorphic computing architectures for deep neural network. DATE 2018: 183-188 - [c53]Giyoung Yang, Taewhan Kim:
Design and algorithm for clock gating and flip-flop co-optimization. ICCAD 2018: 14 - 2016
- [c52]Deokjin Joo, Taewhan Kim:
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. ASP-DAC 2016: 226-231 - [c51]Dongyoun Yi, Taewhan Kim:
Allocation of multi-bit flip-flops in logic synthesis for power optimization. ICCAD 2016: 33 - [c50]Jeongwoo Heo, Taewhan Kim:
Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model. ISVLSI 2016: 42-46 - [c49]Heechun Park, Taewhan Kim:
Synthesizing Asynchronous Circuits toward Practical Use. ISVLSI 2016: 47-52 - 2015
- [c48]Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. ASP-DAC 2015: 484-489 - [c47]Hyungjung Seo, Juyeon Kim, Minseok Kang, Taewhan Kim:
Synthesis for Power-Aware Clock Spines. ICCAD 2015: 126-131 - [c46]Hyungjung Seo, Jeongwoo Heo, Taewhan Kim:
Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing. ISQED 2015: 35-39 - 2014
- [c45]Kitae Park, Geunho Kim, Taewhan Kim:
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs. DATE 2014: 1-4 - 2013
- [c44]Juyeon Kim, Deokjin Joo, Taewhan Kim:
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. DAC 2013: 90:1-90:6 - [c43]Heechun Park, Taewhan Kim:
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. ICCAD 2013: 691-696 - [c42]Taewhan Kim:
Tutorial: Methodology for designing reliable clock networks. SoCC 2013: 141 - 2011
- [c41]Deokjin Joo, Taewhan Kim:
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. DAC 2011: 522-527 - [c40]YongHwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim:
Clock design techniques considering circuit reliability. ISOCC 2011: 142-145 - 2010
- [c39]Tak-Yung Kim, Taewhan Kim:
Clock tree embedding for 3D ICs. ASP-DAC 2010: 486-491 - [c38]Tak-Yung Kim, Taewhan Kim:
Clock tree synthesis with pre-bond testability for 3D stacked IC designs. DAC 2010: 723-728 - [c37]Tak-Yung Kim, Taewhan Kim:
Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. Green Computing Conference 2010: 525-532 - 2009
- [c36]Hochang Jang, Taewhan Kim:
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. DAC 2009: 794-799 - 2006
- [c35]Pilok Lim, Taewhan Kim:
Thermal-aware high-level synthesis based on network flow method. CODES+ISSS 2006: 124-129 - [c34]Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim:
A systematic IP and bus subsystem modeling for platform-based system design. DATE 2006: 560-564 - [c33]Young-Jun Kim, Taewhan Kim:
HW/SW partitioning techniques for multi-mode multi-task embedded applications. ACM Great Lakes Symposium on VLSI 2006: 25-30 - [c32]Taewhan Kim:
Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. RTCSA 2006: 199-206 - 2005
- [c31]Jungeun Kim, Taewhan Kim:
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. DAC 2005: 105-110 - 2004
- [c30]Keoncheol Shin, Taewhan Kim:
An integrated approach to timing-driven synthesis and placement of arithmetic circuits. ASP-DAC 2004: 155-158 - [c29]Yoonseo Choi, Taewhan Kim:
Memory access driven storage assignment for variables in embedded system design. ASP-DAC 2004: 478-481 - [c28]Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim:
Resource-constrained low-power bus encoding with crosstalk delay elimination. ASP-DAC 2004: 834-837 - [c27]Chun-Gi Lyuh, Taewhan Kim:
Memory access scheduling and binding considering energy minimization in multi-bank memory systems. DAC 2004: 81-86 - [c26]Jaewon Seo, Taewhan Kim, Ki-Seok Chung:
Profile-based optimal intra-task voltage scheduling for hard real-time applications. DAC 2004: 87-92 - [c25]Keoncheol Shin, Taewhan Kim:
Leakage power minimization for the synthesis of parallel multiplier circuits. ACM Great Lakes Symposium on VLSI 2004: 166-169 - 2003
- [c24]Yoonseo Choi, Taewhan Kim:
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. DAC 2003: 881-886 - [c23]Junhyung Um, Taewhan Kim:
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. ICCAD 2003: 197-200 - [c22]Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim:
An efficient inverse multiplier/divider architecture for cryptography systems. ISCAS (5) 2003: 149-152 - 2002
- [c21]Junhyung Um, Taewhan Kim:
Layout-aware synthesis of arithmetic circuits. DAC 2002: 207-212 - [c20]Yoonseo Choi, Taewhan Kim:
Address assignment combined with scheduling in DSP code generation. DAC 2002: 225-230 - [c19]Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis for low power. ICCAD 2002: 609-613 - [c18]Junhyung Um, Jae-Hoon Kim, Taewhan Kim:
Layout-driven resource sharing in high-level synthesis. ICCAD 2002: 614-618 - [c17]Unni Narayanan, Ki-Seok Chung, Taewhan Kim:
Enhanced bus invert encodings for low-power. ISCAS (5) 2002: 25-28 - [c16]Yoonseo Choi, Taewhan Kim:
An efficient low-power binding algorithm in high-level synthesis. ISCAS (4) 2002: 321-324 - [c15]Yoonseo Choi, Taewhan Kim:
Address code optimization using code scheduling for digital signal processors. ISCAS (5) 2002: 481-484 - 2001
- [c14]Youngtae Kim, Taewhan Kim:
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. ASP-DAC 2001: 622-628 - [c13]Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu:
A Static Estimation Technique of Power Sensitivity in Logic Circuits. DAC 2001: 215-219 - [c12]Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung:
An accurate evaluation of routing density for symmetrical FPGAs. ACM Great Lakes Symposium on VLSI 2001: 51-55 - [c11]Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung:
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. ICCAD 2001: 137-143 - [c10]Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu:
An Integrated Data Path Optimization for Low Power Based on Network Flow Method. ICCAD 2001: 553-559 - 2000
- [c9]Taewhan Kim, Junhyung Um:
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). ASP-DAC 2000: 313-316 - [c8]Junhyung Um, Taewhan Kim, C. L. Liu:
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC 2000: 98-103 - [c7]Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu:
Behavioral-level partitioning for low power design in control-dominated application. ACM Great Lakes Symposium on VLSI 2000: 156-161 - 1999
- [c6]Junhyung Um, Taewhan Kim, C. L. Liu:
Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD 1999: 410-413 - 1998
- [c5]Taewhan Kim, William Jao, Steven W. K. Tjiang:
Arithmetic Optimization Using Carry-Save-Adders. DAC 1998: 433-438 - 1994
- [c4]Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu:
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. EDAC-ETC-EUROASIC 1994: 586-590 - 1993
- [c3]Taewhan Kim, C. L. Liu:
Utilization of Multiport Memories in Data Path Synthesis. DAC 1993: 298-302 - [c2]Chaeryung Park, Taewhan Kim, C. L. Liu:
Register allocation for data flow graphs with conditional branches and loops. EURO-DAC 1993: 232-237 - 1991
- [c1]Taewhan Kim, Jane W.-S. Liu, C. L. Liu:
A Scheduling Algorithm for Conditional Resource Sharing. ICCAD 1991: 84-87
Reference Works
- 2012
- [r1]Taewhan Kim:
Power Saving by Task-Level Dynamic Voltage Scaling. Handbook of Energy-Aware and Green Computing 2012: 361-383
Coauthor Index
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