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ORCIDDeokjin Joo
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2010 – 2019
- 2017
[j6]Deokjin Joo, Taewhan Kim:
Clock buffer polarity assignment under useful skew constraints. Integr. 57: 52-61 (2017)- [i1]Keunwoo Choi, Deokjin Joo, Juho Kim:
Kapre: On-GPU Audio Preprocessing Layers for a Quick Implementation of Deep Neural Network Models with Keras. CoRR abs/1706.05781 (2017) - 2016
- [j5]Juyeon Kim
, Deokjin Joo, Taewhan Kim:
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. Integr. 52: 91-101 (2016) - [c4]Deokjin Joo, Taewhan Kim:
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. ASP-DAC 2016: 226-231 - 2014
- [j4]Deokjin Joo, Taewhan Kim:
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 423-436 (2014) - 2013
- [j3]Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim:
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 392-405 (2013) - [c3]Juyeon Kim, Deokjin Joo, Taewhan Kim:
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. DAC 2013: 90:1-90:6 - 2012
- [j2]Deokjin Joo, Minseok Kang, Taewhan Kim:
Design Methodologies for Reliable Clock Networks. J. Comput. Sci. Eng. 6(4): 257-266 (2012) - 2011
- [j1]Hochang Jang, Deokjin Joo, Taewhan Kim:
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 96-109 (2011) - [c2]Deokjin Joo, Taewhan Kim:
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. DAC 2011: 522-527 - [c1]YongHwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim:
Clock design techniques considering circuit reliability. ISOCC 2011: 142-145
Coauthor Index
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