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2020 – today
- 2022
[j5]Jeongwoo Heo
, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyumyung Choi:
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1929-1942 (2022)- 2020
- [j4]Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyu-Myung Choi:
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. Integr. 74: 81-92 (2020) - [c14]Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. ASP-DAC 2020: 139-144
2010 – 2019
- 2019
- [c13]Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. ISVLSI 2019: 146-151 - 2012
- [c12]Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
MAPG: Memory access power gating. DATE 2012: 1054-1059 - 2011
- [b1]Kwangok Jeong:
Variability assessment and mitigation in advanced VLSI manufacturing through design-manufacturing co-optimization. University of California, San Diego, USA, 2011 - [c11]Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu:
Stability and scalability in global routing. SLIP 2011: 1-6 - [c10]Kwangok Jeong, Andrew B. Kahng:
Toward PDN resource estimation: A law of general power density. SLIP 2011: 1-6 - 2010
- [j3]Kwangok Jeong, Andrew B. Kahng, Binshan Lin, Kambiz Samadi:
Accurate Machine-Learning-Based On-Chip Router Modeling. IEEE Embed. Syst. Lett. 2(3): 62-66 (2010) - [j2]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1070-1082 (2010) - [j1]Mohit Gupta, Kwangok Jeong, Andrew B. Kahng:
Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1229-1242 (2010) - [c9]Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang:
Toward effective utilization of timing exceptions in design optimization. ISQED 2010: 54-61 - [c8]Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu:
Assessing chip-level impact of double patterning lithography. ISQED 2010: 122-130 - [c7]Kwangok Jeong, Andrew B. Kahng:
Methodology from chaos in IC implementation. ISQED 2010: 885-892
2000 – 2009
- 2009
- [c6]Kwangok Jeong, Andrew B. Kahng:
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. ASP-DAC 2009: 486-491 - [c5]Mohit Gupta, Kwangok Jeong, Andrew B. Kahng:
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. ICCAD 2009: 607-614 - [c4]Kwangok Jeong, Andrew B. Kahng, Hailong Yao:
Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED 2009: 127-134 - [c3]Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu:
Is overlay error more important than interconnect variations in double patterning? SLIP 2009: 3-10 - 2008
- [c2]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC 2008: 516-521 - [c1]Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi:
Quantified Impacts of Guardband Reduction on Design Process Outcomes. ISQED 2008: 790-797
Coauthor Index
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