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Books and Theses
- 1985
[b1]Wu-Tung Cheng:
Testing and Error Detection in Iterative Logic Arrays. University of Illinois Urbana-Champaign, USA, 1985
Journal Articles
- 2022
- [j29]Chong-Siao Ye
, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski:
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2323-2336 (2022) - 2021
- [j28]Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. 9(2): 680-691 (2021) - 2020
- [j27]Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Scan Integrity Tests for EDT Compression. IEEE Des. Test 37(4): 21-26 (2020) - [j26]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng:
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3044-3055 (2020) - 2018
- [j25]Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2087-2097 (2018) - 2016
- [j24]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng:
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test 33(2): 9-16 (2016) - [j23]Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng:
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test 33(6): 23-30 (2016) - 2015
- [j22]Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1836-1846 (2015) - [j21]Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2039-2048 (2015) - [j20]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 466-479 (2015) - [j19]Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1050-1062 (2015) - 2014
- [j18]Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 476-488 (2014) - [j17]Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1258-1268 (2014) - [j16]Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang:
Diagnose Failures Caused by Multiple Locations at a Time. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 824-837 (2014) - 2013
- [j15]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 737-747 (2013) - [j14]Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1265-1273 (2013) - [j13]Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng:
Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1440-1444 (2013) - 2012
- [j12]Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang:
Scan-Based Speed-Path Debug for a Microprocessor. IEEE Des. Test Comput. 29(4): 92-99 (2012) - 2010
- [j11]Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1110-1120 (2010) - 2008
- [j10]Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li:
Survey of Scan Chain Diagnosis. IEEE Des. Test Comput. 25(3): 240-248 (2008) - [j9]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 147-159 (2008) - 2007
- [j8]Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24(5): 476-485 (2007) - 2002
- [j7]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy:
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electron. Test. 18(2): 189-201 (2002) - [j6]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
On Concurrent Test of Core-Based SOC Design. J. Electron. Test. 18(4-5): 401-414 (2002) - 1992
- [j5]Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 198-207 (1992) - [j4]Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu:
Optimal diagnostic methods for wiring interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9): 1161-1166 (1992) - 1990
- [j3]Wu-Tung Cheng, Meng-Lin Yu:
Differential fault simulation for sequential circuits. J. Electron. Test. 1(1): 7-13 (1990) - 1989
- [j2]Wu-Tung Cheng, Tapan J. Chakraborty:
Gentest: An Automatic Test-Generation System for Sequential Circuits. Computer 22(4): 43-49 (1989) - 1987
- [j1]Wu-Tung Cheng, Janak H. Patel:
A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. IEEE Trans. Computers 36(7): 891-895 (1987)
Conference and Workshop Papers
- 2024
- [c133]Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey:
Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage. ITC 2024: 139-148 - 2022
- [c132]Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson:
Industry Evaluation of Reversible Scan Chain Diagnosis. ITC 2022: 420-426 - [c131]Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy:
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS 2022: 1-7 - 2021
- [c130]Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz:
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. ATS 2021: 103-108 - [c129]Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Sameer Chillarige:
Diagnosis and Yield Learning. ITC-Asia 2021: 1 - 2020
- [c128]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski:
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS 2020: 1-2 - [c127]Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada:
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC 2020: 1-10 - [c126]Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng:
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. ITC-Asia 2020: 118-123 - [c125]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng:
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia 2020: 130-135 - 2019
- [c124]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng:
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC 2019: 341-346 - [c123]Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye:
Deep Learning Based Test Compression Analyzer. ATS 2019: 1-6 - [c122]Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz:
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS 2019: 19-24 - [c121]Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy:
A supervised machine learning application in volume diagnosis. ETS 2019: 1-6 - [c120]Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma, Fengju Niu, Junna Zhong, Wen-Lung Hsu:
Reversible Scan Based Diagnostic Patterns. VLSI-DAT 2019: 1-4 - [c119]Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
On Cyclic Scan Integrity Tests for EDT-based Compression. VTS 2019: 1-6 - 2017
- [c118]Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora:
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. ATS 2017: 219-224 - [c117]Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng:
Scan Chain Diagnosis Based on Unsupervised Machine Learning. ATS 2017: 225-230 - [c116]Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy:
Volume diagnosis data mining. ETS 2017: 1-10 - [c115]Yu Huang, Wu-Tung Cheng:
On designing two-dimensional scan architecture for test chips. VLSI-DAT 2017: 1-4 - 2016
- [c114]Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng:
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS 2016: 132-137 - [c113]Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Testing of small delay faults in a clock network. ETS 2016: 1-6 - [c112]Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng:
A wide-range clock signal generation scheme for speed grading of a logic core. HPCS 2016: 125-129 - [c111]Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng:
Online slack-time binning for IO-registered die-to-die interconnects. ITC 2016: 1-8 - 2015
- [c110]Xijiang Lin, Wu-Tung Cheng, Janusz Rajski:
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS 2015: 97-102 - [c109]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng:
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. DATE 2015: 924-927 - [c108]Yu Huang, Wu Yang, Wu-Tung Cheng:
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies. ETS 2015: 1-10 - [c107]Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Monitoring the delay of long interconnects via distributed TDC. ITC 2015: 1-9 - [c106]Wu-Tung Cheng:
Identify problematic layout patterns through volume diagnosis. VLSI-DAT 2015: 1 - [c105]Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng:
A test-application-count based learning technique for test time reduction. VLSI-DAT 2015: 1-4 - [c104]Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke:
Diagnosing timing related cell internal defects for FinFET technology. VLSI-DAT 2015: 1-4 - [c103]Wu-Tung Cheng, Sudhakar M. Reddy:
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. VLSID 2015: 21-23 - 2014
- [c102]Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. ATS 2014: 162-167 - [c101]Huaxing Tang, Brady Benware, Michael Reese, Joseph Caroselli, Thomas Herrmann, Friedrich Hapke, Robert Tao, Wu-Tung Cheng, Manish Sharma:
Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models. ATS 2014: 318-323 - [c100]Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. ETS 2014: 1-2 - [c99]Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung:
Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW 2014: 22-31 - 2013
- [c98]Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
Mid-bond Interposer Wire Test. Asian Test Symposium 2013: 153-158 - [c97]Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
At-speed BIST for interposer wires supporting on-the-spot diagnosis. IOLTS 2013: 67-72 - [c96]Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. ITC 2013: 1-8 - [c95]Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles:
EDT bandwidth management - Practical scenarios for large SoC designs. ITC 2013: 1-10 - [c94]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) scan chain stitching. ITC 2013: 1-10 - [c93]Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng:
Improve speed path identification with suspect path expressions. VLSI-DAT 2013: 1-4 - [c92]Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy:
Distributed dynamic partitioning based diagnosis of scan chain. VTS 2013: 1-6 - 2012
- [c91]Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy:
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. Asian Test Symposium 2012: 7-12 - [c90]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs. Asian Test Symposium 2012: 43-48 - [c89]Wu-Tung Cheng, Feng-Ming Kuo:
Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis. Asian Test Symposium 2012: 271 - [c88]Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia:
A Hybrid Flow for Memory Failure Bitmap Classification. Asian Test Symposium 2012: 314-319 - [c87]Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036 - [c86]Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware:
Improved volume diagnosis throughput using dynamic design partitioning. ITC 2012: 1-10 - [c85]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
A unified method for parametric fault characterization of post-bond TSVs. ITC 2012: 1-10 - 2011
- [c84]Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware:
On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium 2011: 219-225 - [c83]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy:
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT 2011: 217-225 - [c82]Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng:
Deterministic IDDQ diagnosis using a net activation based model. ITC 2011: 1-10 - [c81]Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab:
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC 2011: 1-9 - 2010
- [c80]Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng:
Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC 2010: 493-498 - [c79]Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor:
Emulating and diagnosing IR-drop by using dynamic SDF. ASP-DAC 2010: 511-516 - [c78]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy:
Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium 2010: 94-99 - [c77]Wu-Tung Cheng, Yu Huang:
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. Asian Test Symposium 2010: 255-260 - [c76]Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor:
Full-circuit SPICE simulation based validation of dynamic delay estimation. ETS 2010: 101-106 - [c75]Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz:
Scan based speed-path debug for a microprocessor. ETS 2010: 207-212 - [c74]Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli:
A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD 2010: 162-167 - [c73]Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli:
Test cycle power optimization for scan-based designs. ITC 2010: 134-143 - [c72]Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen:
Case study of scan chain diagnosis and PFA on a low yield wafer. ITC 2010: 818 - 2009
- [c71]Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen:
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. Asian Test Symposium 2009: 35-40 - [c70]Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang:
On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium 2009: 41-46 - [c69]Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng:
At-Speed Scan Test Method for the Timing Optimization and Calibration. Asian Test Symposium 2009: 430-433 - [c68]Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy:
Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE 2009: 1000-1005 - [c67]Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai:
Speed-Path Debug Using At-Speed Scan Test Patterns. ETS 2009: 11-16 - 2008
- [c66]Chen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma:
Hyperactive Faults Dictionary to Increase Diagnosis Throughput. ATS 2008: 173-178 - [c65]Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake:
Enhancing Transition Fault Model for Delay Defect Diagnosis. ATS 2008: 179-184 - [c64]Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng:
A Robust Automated Scan Pattern Mismatch Debugger. ATS 2008: 309-314 - [c63]Yu Huang, Wu-Tung Cheng, Ruifeng Guo:
Diagnose Multiple Stuck-at Scan Chain Faults. ETS 2008: 105-110 - [c62]Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng:
Detection and Diagnosis of Static Scan Cell Internal Defect. ITC 2008: 1-10 - [c61]Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng:
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10 - [c60]Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann:
Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. ITC 2008: 1-9 - [c59]Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
Reducing Scan Shift Power at RTL. VTS 2008: 139-146 - [c58]Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng:
Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186 - 2007
- [c57]Ruifeng Guo, Yu Huang, Wu-Tung Cheng:
Fault Dictionary Based Scan Chain Failure Diagnosis. ATS 2007: 45-52 - [c56]Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich:
A RTL Testability Analyzer Based on Logical Virtual Prototyping. ATS 2007: 121-124 - [c55]Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg:
Scan Diagnosis and Its Successful Industrial Applications. ATS 2007: 215 - [c54]Huaxing Tang, Chen Liu, Wu-Tung Cheng, Sudahkar M. Reddy, Wei Zou:
Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead. ATS 2007: 281-287 - [c53]Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht:
Programmable Scan-Based Logic Built-In Self Test. ATS 2007: 371-377 - [c52]Ruifeng Guo, Yu Huang, Wu-Tung Cheng:
A complete test set to diagnose scan chain failures. ITC 2007: 1-10 - [c51]Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann:
Diagnose compound scan chain and system logic defects. ITC 2007: 1-10 - [c50]Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang:
Interconnect open defect diagnosis with minimal physical information. ITC 2007: 1-10 - [c49]Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann:
Faster defect localization in nanometer technology based on defective cell diagnosis. ITC 2007: 1-10 - [c48]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS 2007: 225-230 - 2006
- [c47]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Interconnect Open Defect Diagnosis with Physical Information. ATS 2006: 203-209 - [c46]Xiaogang Du, Nilanjan Mukherjee, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy:
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. ATS 2006: 287-292 - [c45]Andreas Leininger, Ajay Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, Randy Klingenberg, Wu Yang:
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format. ATS 2006: 360-368 - [c44]Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill:
Signature Based Diagnosis for Logic BIST. ITC 2006: 1-9 - [c43]Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen:
Diagnosis with Limited Failure Information. ITC 2006: 1-10 - [c42]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10 - [c41]Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich:
Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC 2006: 1-9 - [c40]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
On Methods to Improve Location Based Logic Diagnosis. VLSI Design 2006: 181-187 - 2005
- [c39]Yu Huang, Wu-Tung Cheng, Greg Crowell:
Using fault model relaxation to diagnose real scan chain defects. ASP-DAC 2005: 1176-1179 - [c38]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Bridge Defect Diagnosis with Physical Information. Asian Test Symposium 2005: 248-253 - [c37]Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press:
Achieving High Test Quality with Reduced Pin Count Testing. Asian Test Symposium 2005: 312-317 - [c36]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484 - [c35]Yu Huang, Wu-Tung Cheng, Janusz Rajski:
Compressed pattern diagnosis for scan chain failures. ITC 2005: 8 - [c34]Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy:
Full-speed field-programmable memory BIST architecture. ITC 2005: 9 - [c33]Manish Sharma, Wu-Tung Cheng:
X-filter: filtering unknowns from compacted test responses. ITC 2005: 9 - [c32]Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai:
Compression mode diagnosis enables high volume monitoring diagnosis flow. ITC 2005: 10 - [c31]Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy:
Full-speed field programmable memory BIST supporting multi-level looping. MTDT 2005: 67-71 - 2004
- [c30]Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski:
Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209 - [c29]Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung:
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. DATE 2004: 1072-1077 - [c28]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66 - [c27]Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee:
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900 - [c26]Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel:
Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205 - [c25]Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk:
Memory BIST Using ESP. VTS 2004: 243-248 - 2003
- [c24]Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung:
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. Asian Test Symposium 2003: 44-49 - [c23]Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng:
Testing Delay Faults in Embedded CAMs. Asian Test Symposium 2003: 378-383 - [c22]Yu Huang, Wu-Tung Cheng:
Using embedded infrastructure IP for SOC post-silicon verification. DAC 2003: 674-677 - [c21]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy:
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104 - [c20]Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung:
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC 2003: 319-328 - [c19]Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai:
BIST for Deep Submicron ASIC Memories with High Performance Application. ITC 2003: 386-392 - [c18]Wu-Tung Cheng:
Silicon Diagnosis. ITC 2003: 1305 - 2002
- [c17]Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng:
Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium 2002: 405-410 - [c16]Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan:
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82 - [c15]Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy:
Constraint Driven Pin Mapping for Concurrent SOC Testing. ASP-DAC/VLSI Design 2002: 511-516 - 2001
- [c14]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265- - [c13]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy:
Effect of RTL coding style on testability. CICC 2001: 255-258 - [c12]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy:
On RTL scan design. ITC 2001: 728-737 - 2000
- [c11]Wu-Tung Cheng:
Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. Asian Test Symposium 2000: 10- - [c10]Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy:
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212 - 1999
- [c9]Wu-Tung Cheng:
High time for high level ATPG. ITC 1999: 1113 - 1996
- [c8]Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski:
A Universal Technique for Accelerating Simulation of Scan Test Patterns. ITC 1996: 135-141 - 1990
- [c7]Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC 1990: 535-540 - [c6]Wu-Tung Cheng, Janak H. Patel:
PROOFS: a super fast fault simulator for sequential circuits. EURO-DAC 1990: 475-479 - [c5]Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu:
Diagnosis for wiring interconnects. ITC 1990: 565-571 - 1989
- [c4]Wu-Tung Cheng, Meng-Lin Yu:
Differential Fault Simulation - a Fast Method Using Minimal Memory. DAC 1989: 424-428 - 1988
- [c3]Wu-Tung Cheng:
Split Circuit Model for Test Generation. DAC 1988: 96-101 - [c2]Wu-Tung Cheng:
The BACK algorithm for sequential test generation. ICCD 1988: 66-69 - 1985
- [c1]Wu-Tung Cheng, Janak H. Patel:
Multiple-Fault Detection in Iterative Logic Arrays. ITC 1985: 493-499
Coauthor Index
[j26] [j20] [j19] [j16] [j11] [j10] [j7] [j6] [c129] [c128] [c127] [c125] [c124] [c123] [c120] [c117] [c115] [c108] [c99] [c95] [c94] [c92] [c88] [c86] [c79] [c77] [c76] [c73] [c72] [c71] [c70] [c63] [c62] [c59] [c57] [c56] [c55] [c52] [c51] [c43] [c39] [c35] [c30] [c29] [c24] [c22] [c21] [c20] [c17] [c16] [c15] [c14] [c13] [c12]
Kun-Han Tsai
aka: Kun-Han Hans Tsai
aka: Kun-Han Hans Tsai
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