"Circuit and Methodology for Testing Small Delay Faults in the Clock Network."

Shaofu Yang et al. (2018)

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DOI: 10.1109/TCAD.2018.2789779

access: closed

type: Journal Article

metadata version: 2020-09-24

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Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2087-2097 (2018)

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