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2010 – 2019
- 2013
[c8]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht:
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium 2013: 201-206
2000 – 2009
- 2008
- [c7]Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393 - 2007
- [c6]Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht:
Programmable Scan-Based Logic Built-In Self Test. ATS 2007: 371-377 - 2006
- [c5]Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill:
Signature Based Diagnosis for Logic BIST. ITC 2006: 1-9 - 2005
- [c4]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484 - 2004
- [c3]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66 - [c2]Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht:
Embedded Test for Low Cost Manufacturing. VLSI Design 2004: 21-23 - [c1]Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel:
Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205 - 2003
- [j1]Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli:
High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. 20(5): 17-25 (2003)
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