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ORCIDMichinobu Nakao
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2010 – 2019
- 2013
[j2]Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko:
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. IEICE Trans. Electron. 96-C(1): 108-114 (2013)- 2010
- [j1]Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki:
Reduction of Area per Good Die for SoC Memory Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2463-2471 (2010)
2000 – 2009
- 2008
- [c9]Wu-Tung Cheng, Brady Benware, Ruifeng Guo
, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake:
Enhancing Transition Fault Model for Delay Defect Diagnosis. ATS 2008: 179-184 - [c8]Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki:
Hardware Overhead Reduction for Memory BIST. ITC 2008: 1 - 2002
- [c7]Kazumi Hatayama, Michinobu Nakao, Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297 - [c6]Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo:
Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012 - 2001
- [c5]Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo:
Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244- - 2000
- [c4]Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo:
A BIST approach for very deep sub-micron (VDSM) defects. ITC 2000: 283-291
1990 – 1999
- 1999
- [c3]Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada:
Low overhead test point insertion for scan-based BIST. ITC 1999: 348-357 - 1997
- [c2]Michinobu Nakao, Kazumi Hatayama, Isao Higashi:
Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium 1997: 359- - 1995
- [c1]Hiroshi Date, Michinobu Nakao, Kazumi Hatayama:
A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium 1995: 252-258
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