"Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via ..."

Yu-Hsiang Lin et al. (2013)

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DOI: 10.1109/TCAD.2012.2236837

access: closed

type: Journal Article

metadata version: 2020-09-24

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Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 737-747 (2013)

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