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ORCIDJournal of Circuits, Systems, and Computers, Volume 26
Volume 26, Number 1, January 2017
- Tripurari Sharan, Vijaya Bhadauria
:
Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain. 1750001:1-1750001:25 - Anil Singh, Ayushi Goel, Alpana Agarwal:
A Digital-Based Low-Power Fully Differential Comparator. 1750002:1-1750002:12 - Yun Zhang, Yiqiang Zhao, Peng Dai:
Study of Split Capacitor DAC Mismatch and Calibration in SAR-ADC. 1750003:1-1750003:19 - Ayub Shokrollahi, Babak Mazloom-Nezhad Maybodi:
An Energy-Efficient Clustering Algorithm Using Fuzzy C-Means and Genetic Fuzzy System for Wireless Sensor Network. 1750004:1-1750004:22 - Paulo David Battaglin, Gilmar Barreto:
Kalman Filtering Solution Converges on a Personal Computer. 1750005:1-1750005:17 - Xinsheng Wang, Chenxu Wang, Mingyan Yu:
The Minimum Norm Least-Squares Solution in Reduction by Krylov Subspace Methods. 1750006:1-1750006:18 - Shunji Nakata, Masaki Ono, Masato Sakitani:
An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor. 1750007:1-1750007:15 - Pichid Kittisuwan, C. Chinrungrueng:
Differential Form of Bivariate MMSE Estimator Based on Gaussian Noise. 1750008:1-1750008:12 - Xin Li, Jin Sun:
Genetic Algorithm-Based Multi-Objective Optimization for Statistical Yield Analysis Under Parameter Variations. 1750009:1-1750009:21 - Atul Kumar, Bhartendu Chaturvedi:
Novel CMOS Current Inverting Differential Input Transconductance Amplifier and Its Application. 1750010:1-1750010:16 - Tuba Nur Gul, Ali Kircay:
The Design of Fifth-Order Butterworth Lowpass Log-Domain Filter for Bluetooth/Wi-Fi Receiver Using Signal Flow Graph Method. 1750011:1-1750011:17 - Farzad Mohammadzadeh Shahir, Ebrahim Babaei, Murtaza Farsadi:
A New Structure for Nonisolated Boost DC-DC Converter. 1750012:1-1750012:26 - Mehmet Sagbas, Umut Engin Ayten, Herman Sedef, Shahram Minaei:
Modified Gorski-Popiel Technique and Synthetic Floating Transformer Circuit Using Minimum Components. 1750013:1-1750013:21 - M. C. Parameshwara, H. C. Srinivasaiah:
Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. 1750014:1-1750014:15 - Ismail Koyuncu, Ibrahim Sahin, Clay Gloster, Namik Kemal Saritekin:
A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System. 1750015:1-1750015:21 - Junlong Zhou, Min Yin, Zhifang Li, Kun Cao, Jianming Yan, Tongquan Wei, Mingsong Chen, Xin Fu:
Fault-Tolerant Task Scheduling for Mixed-Criticality Real-Time Systems. 1750016:1-1750016:17 - Zeshi Yuan, Hongtao Li, Xiaohua Zhu:
A Useful Chaotic Family with Single Linearity and Circuit Implementation Based on FPGA. 1750017:1-1750017:21 - Nahid Mirzaie, Hossein Shamsi, Gyung-Su Byun:
Automatic Design and Yield Enhancement of Data Converters. 1750018:1-1750018:19
Volume 26, Number 2, February 2017
- Nesrine Toubaline, Djamel Bennouar, Ali Mahdoum:
A Classification and Evaluation Framework for NoC Mapping Strategies. 1730001:1-1730001:44
- Nazar Abbas Saqib, Muhammad Zia, Hasan Mahmood, Muazzam Ali Khan:
On Generating High-Quality Random Numbers. 1750019:1-1750019:21 - T. R. Rajalakshmi, R. Sudhakar:
Impact of Single Event Upset on Voltage and Current Behaviors of CNTFET SRAM and a Comparison with CMOS SRAM. 1750020:1-1750020:14 - Ateeq-Ur-Rehman Shaheen, Fawnizu Azmadi Hussin, Nor Hisham Hamid:
A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits. 1750021:1-1750021:26 - Siyuan Xu, Han Zhuang, Xin Fu, Junlong Zhou, Mingsong Chen:
GPU-Based Fluid Motion Estimation Using Energy Constraint. 1750022:1-1750022:20 - Minoh Son, Changkun Park:
Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level. 1750023:1-1750023:9 - Godpromesse Kenné, Clotaire Thierry Sanjong, Eustace Mbaka Nfah:
Adaptive PI Control Strategy for a Self-Excited Induction Generator Driven by a Variable Speed Wind Turbine. 1750024:1-1750024:36 - Erkan Yüce:
DO-CCII/DO-DVCC Based Electronically Fine Tunable Quadrature Oscillators. 1750025:1-1750025:17 - Mehmet Serhat Odabas, Nurettin Senyer, Gökhan Kayhan, Erhan Ergun:
Estimation of Chlorophyll Concentration Index at Leaves using Artificial Neural Networks. 1750026:1-1750026:13 - Chia-Hung Chang, Cihun-Siyong Alex Gong, Jian-Chiun Liou, Yu-Lin Tsou, Feng-Lin Shiu, Hwann-Kaeo Chiou, Po-Hsun Tu:
A 260-μW Down-Conversion Demodulator for MICS-Band Receiver. 1750027:1-1750027:10 - Cheng-Hung Lin, Tzu-Hsuan Huang, Shu-Yen Lin, Yu-Hsuan Lee:
Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme. 1750028:1-1750028:19 - Zehra Gulru Cam, Herman Sedef:
A New Floating Memristance Simulator Circuit Based on Second Generation Current Conveyor. 1750029:1-1750029:15 - Pankaj Kumar, Rajender Kumar Sharma:
Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing. 1750030:1-1750030:18 - Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Two-Run RAM March Testing with Address Decimation. 1750031:1-1750031:17 - Hechmi Ben Azza, Mongi Moujahed, Mohamed Jemli, Mohamed Boussak:
Implementation of Improved Sliding Mode Observer and Fault Tolerant Control for a PMSM Drive. 1750032:1-1750032:16 - Tian-Bo Deng:
Stability-Guaranteed Two-Phase Design of Odd-Order Variable-Magnitude Digital Filters. 1750033:1-1750033:13 - J. Sangeetha, P. Renuga:
Recurrent ANFIS-Coordinated Controller Design for Multimachine Power System with FACTS Devices. 1750034:1-1750034:14 - Stefan Leitner, Haibo Wang, Spyros Tragoudas:
Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges. 1750035:1-1750035:21
Volume 26, Number 3, March 2017
- A. Karthikeyan, P. S. Mallick:
Optimization Techniques for CNT Based VLSI Interconnects - A Review. 1730002:1-1730002:15 - S. Balamurugan, Partha Sharathi Mallick:
Error Compensation Techniques for Fixed-Width Array Multiplier Design - A Technical Survey. 1730003:1-1730003:31
- Mousumi Bhanja, Baidyanath Ray:
Design of Configurable gm-C Biquadratic Filter. 1750036:1-1750036:19 - Xiaofeng Zhou, Lu Liu, Zhangming Zhu:
A Fault-Tolerant Deflection Routing for Network-on-Chip. 1750037:1-1750037:19 - V. P. Singh, Dharma Pal Singh Chauhan, Sugandh P. Singh, Tapan Prakash:
On Time Moments and Markov Parameters of Continuous Interval Systems. 1750038:1-1750038:7 - Xinghua Yang, Yue Xing, Fei Qiao, Huazhong Yang:
Multistage Latency Adders Architecture Employing Approximate Computing. 1750039:1-1750039:18 - Arun Kumar Sinha:
A Self-Starting 70 mV-1 V, 65% Peak Efficient, TEG Energy Harvesting Chip with 5 ms Startup Time. 1750040:1-1750040:22 - Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan:
Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. 1750041:1-1750041:12 - Hassan A. Salamy, Semih Aslan:
Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC. 1750042:1-1750042:22 - Ching-Han Chen, Ming-Yi Lin, Wen-Hung Lin:
Designing and Implementing a Lightweight WSN MAC Protocol for Smart Home Networking Applications. 1750043:1-1750043:20 - Hirak Kumar Maity, Santi P. Maity:
FPGA Implementation for Modified RCM-RW on Digital Images. 1750044:1-1750044:25 - Renato J. Cintra, Fábio M. Bayer, Arjuna Madanayake, Uma Sadhvi Potluri, Amila Edirisuriya:
Fast Algorithms and Architectures for 8-Point DST-II/DST-VII Approximations. 1750045:1-1750045:11 - Prachi Palsodkar, Pravin Dakhole, Prasanna Palsodkar:
Reduced Complexity Linearity Improved Threshold Quantized Comparator Based Flash ADC. 1750046:1-1750046:19 - Yiqiang Zhao, Jingshuai Wang, Yun Sheng:
A Mixed Signal DC Offset Cancellation for VGA of Zero-IF Receiver. 1750047:1-1750047:9 - Vida Orduee Niar, Gholamreza Zareh Fatin:
A Low Power Low-Pass Fourth-Order Filter for WiMAX/LTE Receiver in CMOS 45nm Technology. 1750048:1-1750048:15 - Saber Krim, Soufien Gdaim, Abdellatif Mtibaa, Mohamed Faouzi Mimouni:
Implementation on the FPGA of DTC-SVM Based Proportional Integral and Sliding Mode Controllers of an Induction Motor: A Comparative Study. 1750049:1-1750049:32 - Jan Jerabek, Roman Sotner, Josef Polak, Lukas Langhammer, Norbert Herencsar, Roman Prokop, Kamil Vrba:
Resistor-Less Single-Purpose or Reconfigurable Biquads Utilizing Single z-Copy Controlled-Gain Voltage Differencing Current Conveyor. 1750050:1-1750050:21 - Lakhindar Murmu, Sushrut Das:
A Dual-Band Bandpass Filter Using Quad-Mode Resonator for Bluetooth and WLAN Applications. 1750051:1-1750051:11
Volume 26, Number 4, April 2017
- Erkan Yüce, Shahram Minaei:
Commercially Available Active Device Based Grounded Inductor Simulator and Universal Filter with Improved Low Frequency Performances. 1750052:1-1750052:14 - Burhan Khurshid, Roohie Naaz Mir:
Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs. 1750053:1-1750053:29 - M. Kiruba, V. Sumathy:
A Novel HBE-MCM-Based Multiplier Architecture for 8-Point DCT Structure. 1750054:1-1750054:22 - Aymen Ben Hammadi, Mongia Mhiri, Fayrouz Haddad, Sehmi Saad, Kamel Besbes:
An Enhanced Design of Multi-Band RF Band Pass Filter Based on Tunable High-Q Active Inductor for Nano-Satellite Applications. 1750055:1-1750055:20 - Chao Tong, Yu Lian, Yang Zhang, Zhongyu Xie, Xiang Long, Jianwei Niu:
A Novel Real-Time Fall Detection System Based on Real-Time Video and Mobile Phones. 1750056:1-1750056:26 - K. Muthulakshmi, R. M. Sasiraja, V. Suresh Kumar:
The Proper Location and Sizing of Multiple Distributed Generators for Maximizing Voltage Stability Using PSO. 1750057:1-1750057:20 - Uzma Mushtaq, Osman Hasan, Falah R. Awwad:
NoC-Based Implementation of Free Form Deformations in Medical Imaging Registration. 1750058:1-1750058:13 - Yiming Ouyang, Jian Da, Xiumin Wang, Qianqian Han, Huaguo Liang, Gaoming Du:
A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC. 1750059:1-1750059:19 - Chengyao Lv, Huihua Liu, Yuanxing Dong, Fangyuan Li, Yuan Liang:
Using Uniform-Design GEP for Part-of-Speech Tagging. 1750060:1-1750060:14 - G. Thippa Reddy, Neelu Khare:
An Efficient System for Heart Disease Prediction Using Hybrid OFBAT with Rule-Based Fuzzy Logic Model. 1750061:1-1750061:21 - Alessandra Pipino, Marcello De Matteis, Karen Wan, Andrea Baschirotto:
A Simple Algorithm for Specs Definition in Wireless Receivers. 1750062:1-1750062:19 - Lianxi Liu, Yiyang Zhou, Junchao Mu, Xufeng Liao, Zhangming Zhu, Yintang Yang:
A Near-Threshold Voltage Startup Monolithic Boost Converter with Adaptive Sleeping Time Control. 1750063:1-1750063:19 - Shyamapada Mukherjee, Suchismita Roy:
Via-Aware Dogleg Routing Using Boolean Satisfiability. 1750064:1-1750064:24 - Yinshan Liang, Jiangling Lu:
Direct Low Order Rational Approximations for Fractional Order Systems in Narrow Frequency Band: A Fix-Pole Method. 1750065:1-1750065:15 - Lamiche Chaabane, Abdelouahab Moussaoui:
Aligning Multiple Sequences Using an Improved Tabu Search Algorithm. 1750066:1-1750066:13 - Naser Khatti, Massoud Dousti:
A Low Phase Noise LC Quadrature VCO Using Impulse Shaping Based on Gaussian Pulse Generator. 1750067:1-1750067:13 - Jaspal Singh Khinda, Malay Ranjan Tripathy, Deepak Gambhir:
Multi-Edged Wide-Band Rectangular Microstrip Fractal Antenna Array for C- and X-Band Wireless Applications. 1750068:1-1750068:25 - Sergio Saponara, Filippo Giannetti, Bruno Neri:
Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G. 1750069:1-1750069:27
Volume 26, Number 5, May 2017
- Metin Sengül:
Broadband Matching via Unequal Length Cascaded Transmission Lines. 1750070:1-1750070:12 - Kamil Zeberga, Rize Jin, Hyung-Ju Cho, Tae-Sun Chung:
A Safe-Region Approach to a Moving k-RNN Queries in a Directed Road Network. 1750071:1-1750071:18 - Min-Shiang Hwang, Tsuei-Hung Sun, Cheng-Chi Lee:
Achieving Dynamic Data Guarantee and Data Confidentiality of Public Auditing in Cloud Storage Service. 1750072:1-1750072:16 - Abdullah El-Bayoumi, Hassan Mostafa, Ahmed M. Soliman:
A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit. 1750073:1-1750073:35 - Hassan Fathabadi:
Comparative Study Between Two Novel BJT-DVCC and CMOS-DVCC. 1750074:1-1750074:10 - Najam Muhammad Amin, Lianfeng Shen, Zhigong Wang, Muhammad Ovais Akhter, Muhammad Tariq Afridi:
60 GHz-Band Low-Noise Amplifier. 1750075:1-1750075:17 - Noura Ben Ameur:
A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit. 1750076:1-1750076:13 - Anush Bekal, Shabi Tabassum, Manish Goswami:
Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC. 1750077:1-1750077:25 - E. V. V. Cambero, C. E. Capovilla, Ivan Roberto Santana Casella, R. R. Munoz, H. X. Araujo:
A CMOS LNA Partially Degenerated Topology Proposal Using Active Inductors. 1750078:1-1750078:15 - Saroja S. Bhusare, V. S. Kanchana Bhaaskaran:
Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique. 1750079:1-1750079:12 - Nadia Gargouri, Dalenda Ben Issa, Zied Sakka, Abdennaceur Kachouri, Mounir Samet:
Design and Optimization of Differential Ring Oscillator for IR-UWB Applications in 0.18 μm CMOS Technology. 1750080:1-1750080:15 - Adam Milik, Edward Hrynkiewicz:
Nonlinearity Measurement of a Voltage Ramp Using a Digital Technique. 1750081:1-1750081:15 - Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Zahra Zareei, Seyedeh Mohtaram Daryabari:
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. 1750082:1-1750082:15 - Yuen-Haw Chang, Chun-Hung Wang:
Design and Analysis of AMSCC for Piezoelectric Energy Harvesting. 1750083:1-1750083:21 - Pankaj Kumar, Rajender Kumar Sharma:
An Energy Efficient Logic Approach to Implement CMOS Full Adder. 1750084:1-1750084:20 - Nasser Erfani Majd, Hassan Ghafoori Fard, Abbas Mohammadi:
Coding Efficiency and Bandwidth Enhancement in Polar Delta-Sigma Modulator Transmitter Using Quantization Noise Reduction and Parallel Processing Techniques. 1750085:1-1750085:23 - Boris Ryabko, Anton Rakitskiy:
An Analytic Method for Estimating the Computation Capacity of Computing Devices. 1750086:1-1750086:13 - Igor Lemberski:
Asynchronous Logic Implementation Based on Factorized DIMS. 1750087:1-1750087:9
Volume 26, Number 6, June 2017
- Yong-An Li:
Systematic Synthesis of High-Q T-T Filters Employing CCCIIs. 1750088:1-1750088:8 - R. Velmurugan, K. Mahadevan:
A Novel RRR-SVPWM-Based Speed Controlling Mechanism for Brushless DC Motor. 1750089:1-1750089:24 - B. R. Lin:
ZVS Converter with Full-Bridge and Half-Bridge Circuits: Analysis, Design and Implementation. 1750090:1-1750090:13 - Linwei Niu, Wei Li:
Energy-Efficient Scheduling for Embedded Real-Time Systems Using Threshold Work-Demand Analysis. 1750091:1-1750091:36 - J. N. Chandra Sekhar, G. V. Marutheswar:
Direct Torque Control of Induction Motor Using Enhanced Firefly Algorithm - ANFIS. 1750092:1-1750092:22 - Sudhanshu Maheshwari, Deepak Agrawal:
Cascadable and Tunable Analog Building Blocks Using EX-CCCII. 1750093:1-1750093:16 - Phatsagul Thitimahatthanagusol, Charinsak Saetiaw, Thanaset Thosdeekoraphat, Chanchai Thongsopa, Saksit Summart:
CCCIIs-Based First-Order All-Pass Filter and Quadrature Oscillators. 1750094:1-1750094:18 - Vigneswaran Narayanamurthy, Sujatha Lakshminarayanan, Mohamed Yacin Sikkandar, Fahmi Samsuri:
Design Optimization and Analysis of Proof Mass Actuation for MEMS Accelerometer: A Simulation Study. 1750095:1-1750095:10 - Amit Bage, Sushrut Das:
Compact Triple-Band Waveguide Bandpass Filter Using Concentric Multiple Complementary Split Ring Resonators. 1750096:1-1750096:12 - Alexandru Amaricai, Ovidiu Sicoe, Oana Boncalo:
On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers. 1750097:1-1750097:13 - Mustafa Konal, Firat Kaçar:
MOS Only Grounded Active Inductor Circuits and Their Filter Applications. 1750098:1-1750098:17 - Hamid Reza Baghaee, Mojtaba Mirsalim, Gevork B. Gharehpetian, Heidar Ali Talebi:
Eigenvalue, Robustness and Time Delay Analysis of Hierarchical Control Scheme in Multi-DER Microgrid to Enhance Small/Large-Signal Stability Using Complementary Loop and Fuzzy Logic Controller. 1750099:1-1750099:34 - Rohith Krishnan Pilla, S. Krishnakumar:
An Approach Towards Design of Analog Integrated Circuits Based on Fixator-Norator Pair. 1750100:1-1750100:19 - Mohammad Rahimi, Behrad Soleymani, Farrokh Aminifar, Amin Gholami:
A New Methodology for Circuit Analysis with Reverse Analysis Capability. 1750101:1-1750101:24 - Manodipan Sahoo, Hafizur Rahaman:
Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects. 1750102:1-1750102:21 - Pankaj Garg, Singara Singh Kasana, Geeta Kasana:
Block-Based Reversible Data Hiding Using Histogram Shifting and Modulus Operator for Digital Images. 1750103:1-1750103:17 - Ramya Vijay, T. Rama Rao, Revathi Venkataraman:
Concurrent Multi-Band Low-Noise Amplifier. 1750104:1-1750104:11 - Ebrahim Babaei, Zahra Saadatizadeh, Behnam Mohammadi-Ivatloo:
A New Interleaved Bidirectional Zero Voltage Switching DC/DC Converter with High Conversion Ratio. 1750105:1-1750105:25
Volume 26, Number 7, July 2017
- Muhanad Almawlawe, Darko Mitic, Dragan Antic, Zoran Icic:
An Approach to Microcontroller-Based Realization of Boost Converter with Quasi-Sliding Mode Control. 1750106:1-1750106:16 - Raahat Devender Singh, Naveen Aggarwal:
Optical Flow and Prediction Residual Based Hybrid Forensic System for Inter-Frame Tampering Detection. 1750107:1-1750107:37 - Yuzhuo Pan, Chen Lv, Shanhe Su, Jincan Chen:
Intelligent Control Circuit Integral with Pattern Recognition Techniques for High-Pressure Sodium Lamps. 1750108:1-1750108:15 - Dongmei Zhang, Jianping Liao, Xiaohui Huang, Jiaqi Jin:
A Multifractal-Guided Multilevel Surrogate Model-Based Evolutionary Algorithm for Expensive Multiobjective Problems. 1750109:1-1750109:18 - Md. Haidar Sharif:
An Eigenvalue Approach to Detect Flows and Events in Crowd Videos. 1750110:1-1750110:50 - Jie Wang, Jiwei Liu:
Fault-Tolerant Strategy for Real-Time System Based on Evolvable Hardware. 1750111:1-1750111:18 - Surachoke Thanapitak, Prajuab Pawarangkoon, Chutham Sawigun:
A Flipped Voltage Follower Second-Order Bandpass Filter. 1750112:1-1750112:10 - Jingru Sun, Pan Huang, Yichuang Sun:
A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators. 1750113:1-1750113:13 - M. Srinivasan, G. M. Tamilselvan:
VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier. 1750114:1-1750114:22 - Cheng Huang, Zhilun Lin, Jianhui Wu, Chao Chen:
A Low Offset Dynamic Comparator with Offset Elimination Circuit. 1750115:1-1750115:7 - B. B. Zaidan, A. A. Zaidan:
Software and Hardware FPGA-Based Digital Watermarking and Steganography Approaches: Toward New Methodology for Evaluation and Benchmarking Using Multi-Criteria Decision-Making Techniques. 1750116:1-1750116:27 - Hongmei Chen, Li Wang, Ting Li, Lin He, Fujiang Lin:
A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path. 1750117:1-1750117:13 - Dengbao Liu, Lin He, Fujiang Lin, Ting Li, Yu-Kai Chou:
A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications. 1750118:1-1750118:16 - Chunguang Ma, Lei Zhang, Songtao Yang, Xiaodong Zheng:
Hiding Yourself Behind Collaborative Users When Using Continuous Location-Based Services. 1750119:1-1750119:25 - Thanat Nonthaputha, Montree Kumngern:
Programmable Universal Filters Using Current Conveyor Transconductance Amplifiers. 1750121:1-1750121:23 - Fatma Sbiaa, Sonia Kotel, Zeghid Medien, Rached Tourki, Mohsen Machhout, Adel Baganne:
High-Level Implementation of a Chaotic and AES Based Crypto-System. 1750122:1-1750122:23 - N. Poornima, V. S. Kanchana Bhaaskaran:
Design and Implementation of 32-Bit High Valency Jackson Adders. 1750123:1-1750123:18 - Bahman Arasteh:
Improving the Resiliency of Software Against Soft-Errors Without External Redundancy and Performance Overhead. 1750124:1-1750124:28 - Malgorzata Kolopienczyk, Larysa Titarenko, Alexander Barkalov:
Design of EMB-Based Moore FSMs. 1750125:1-1750125:23
Volume 26, Number 8, August 2017
- Andreas Steininger, Adam Pawlak, Viera Stopjaková:
Foreword. 1702001:1-1702001:1 - Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Sequential Test Decompressors with Fast Tester Bits Wide-Spreading. 1740001:1-1740001:16 - Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design. 1740002:1-1740002:23 - Daniel Arbet, Viera Stopjaková, Martin Kovác, Lukás Nagy, Matej Rakus, Michal Sovcik:
130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications. 1740003:1-1740003:19 - Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. 1740004:1-1740004:19 - Juraj Brenkus, Viera Stopjaková, Viera Cernanová, Daniel Arbet, Lukás Nagy, Vladimír Sedlák:
A Novel Method Towards Time-Efficient Fault Analysis of Analog and Mixed-Signal Circuits. 1740005:1-1740005:20 - Christian Gleichner, Heinrich Theodor Vierhaus:
Test and Diagnosis of Automotive Embedded Processors via High-Speed Standard Interfaces. 1740006:1-1740006:17 - Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Microprocessor Testing: Functional Meets Structural Test. 1740007:1-1740007:18 - Dmitry Osipov, Serge Strokov, Andreas K. Kreiter, Andreas Schander, Tobias Teßmann, Walter Lang, Steffen Paul:
8-Channel Neural Stimulation ASIC for Epidural Visual Cortex Stimulation. 1740008:1-1740008:19 - Aitzan Sari, Mihalis Psarakis:
A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors. 1740009:1-1740009:21 - Thomas Polzer, Andreas Steininger:
A Model for the Metastability Delay of Sequential Elements. 1740010:1-1740010:22
Volume 26, Number 9, September 2017
- Lianping Guo, Feng Tan, Peng Zhang, Hao Zeng:
Decomposing Numerically Controlled Oscillator in Parallel Digital Down Conversion Architecture. 1750126:1-1750126:14 - Gongyuan Zhao, Mao Ye, Yiqiang Zhao, Kai Hu, Ruishan Xin:
A High Order Curvature-Compensated Bandgap Voltage Reference with a Novel Error Amplifier. 1750127:1-1750127:15 - Babak Montazer, Utpal Sarma:
Modeling and Analysis the Effect of PZT Area on Square Shaped Substrate for Power Enhancement in MEMS Piezoelectric Energy Harvester. 1750128:1-1750128:22 - Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini:
VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. 1750129:1-1750129:26 - Ahmet Abaci, Erkan Yüce:
A New DVCC+ Based Second-Order Current-Mode Universal Filter Consisting of Only Grounded Capacitors. 1750130:1-1750130:18 - Nariman A. Khalil, Rania F. Ahmed, Rania Ahmed Abul Seoud, Ahmed M. Soliman:
New Op-Amp Circuits Realizations Using Genetic Algorithm. 1750131:1-1750131:24 - Sungkyung Park, Chester Sungchung Park:
Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications. 1750132:1-1750132:24 - R. Balamurugan, R. Nithya:
Solar PV Based Shunt Active Filter with p-q Theory Control for Improvement of Power Quality. 1750133:1-1750133:13 - Jun-Da Chen, Song-Hao Wang:
A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology. 1750134:1-1750134:13 - Ranjan Kumar Barik, Manoranjan Pradhan, Rutuparna Panda:
Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation. 1750135:1-1750135:18 - Shu Li, Zezhou Sun, Xiaofei Zhang, Weiyang Chen, Dazhuan Xu:
Joint DOA and Frequency Estimation for Linear Array with Compressed Sensing PARAFAC Framework. 1750136:1-1750136:22 - Vijay Kumar Sharma:
Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit. 1750137:1-1750137:19 - Zahra Jeddi, Ahmed K. F. Khattab, Esmaeil Amini, Magdy A. Bayoumi:
Redundant Bit Security in RFIDs: Architecture Design and Security Performance Evaluation. 1750138:1-1750138:25 - Chao Liu, Zheng Yang, Dihua Sun, Xiaoyang Liu, Wanping Liu:
Synchronization of Chaotic Systems with Time Delays via Periodically Intermittent Control. 1750139:1-1750139:20 - Abdullah Yesil, Firat Kaçar:
A New Method for Increasing Quality Factor in Active Filters. 1750140:1-1750140:16 - Soufiane Oukili, Seddik Bri:
Hardware Implementation of AES Algorithm with Logic S-box. 1750141:1-1750141:19 - Ilias Dimeas, Georgia Tsirimokou, Costas Psychalinos, Ahmed S. Elwakil:
Experimental Verification of Fractional-Order Filters Using a Reconfigurable Fractional-Order Impedance Emulator. 1750142:1-1750142:23 - Muhammad-Yasir Masood Mirza, Ghufran Ahmed, Noor Muhammad Khan:
Model-Based Adaptive Transmission Power Control (MATPoC) for Wireless Sensor Networks in Fading Environment. 1750143:1-1750143:34 - Carlos Sánchez-López, Miguel Ángel Carrasco-Aguilar, F. E. Morales-Lopez:
A SPICE-Compatible Nonlinear CCII Macromodel. 1750144:1-1750144:8 - Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya, Bandan Kumar Bhoi:
Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA. 1750145:1-1750145:26
Volume 26, Number 10, October 2017
- Suresh Alapati, Sreehari Rao Patri, K. S. R. Krishna Prasad:
An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance. 1750146:1-1750146:35 - Rohollah Abdollahi:
Design and Experimental Verification of 20-Pulse AC-DC Converter for Retrofit Applications and Harmonic Mitigation. 1750147:1-1750147:17 - Zhiyuan Gao, Yiming Zhou, Jiangtao Xu, Huiying Liu, Jing Gao:
High Dynamic Range Low Distortion PWM Readout Method with Self-Adjusted Reference for Digital Pixel Sensors. 1750148:1-1750148:20 - Lixia Zheng, Huan Hu, Ziqing Weng, Qun Yao, Jin Wu, Weifeng Sun:
Compact Active Quenching Circuit for Single Photon Avalanche Diodes Arrays. 1750149:1-1750149:14 - Sedigheh Farhadtoosky, Ali Jahanian:
Customized Placement Algorithm of Nanoscale DNA Logic Circuits. 1750150:1-1750150:14 - Jassem Mtimet, Hamid Amiri:
A Combined Layer-Based Approach for the Segmentation of Document Images. 1750152:1-1750152:18 - Dawei Li, Dongsheng Liu, Xuecheng Zou, Ke Yao, Chaojian Kang, Huarong Zeng:
A Low-Cost RFID Regulator Insensitive to Temperature and Supply Voltage Variations. 1750153:1-1750153:23 - Armin Belghadr, Ali Jahanian:
Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area. 1750154:1-1750154:25 - Biplab Bhattacharyya, Saurav Raj:
Differential Evolution Technique for the Optimization of Reactive Power Reserves. 1750155:1-1750155:20 - Erdem Alkim, Sedat Akleylek, Erdal Kiliç:
A Modified Parallel Learning Vector Quantization Algorithm for Real-Time Hardware Applications. 1750156:1-1750156:14 - Jan Jerabek, Roman Sotner, Jan Dvorak, Josef Polak, David Kubánek, Norbert Herencsar, Jaroslav Koton:
Reconfigurable Fractional-Order Filter with Electronically Controllable Slope of Attenuation, Pole Frequency and Type of Approximation. 1750157:1-1750157:21 - Wen Hu, Akif Akgul, Chunbiao Li, Taicheng Zheng, Peng Li:
A Switchable Chaotic Oscillator with Two Amplitude-Frequency Controllers. 1750158:1-1750158:12 - Biao Hu, Kai Huang, Gang Chen, Long Cheng, Dongkun Han, Alois C. Knoll:
Schedulability Analysis Towards Arbitrarily Activated Tasks in Mixed-Criticality Systems. 1750159:1-1750159:31 - Lobna A. Said, Ahmed G. Radwan, Ahmed H. Madian, Ahmed M. Soliman:
Three Fractional-Order-Capacitors-Based Oscillators with Controllable Phase and Frequency. 1750160:1-1750160:22 - Qi Liu, Lidan Wang, Jiu Yang, Yan Wang, Shukai Duan:
Fusion of Image Storage and Operation Based on Ag-Chalcogenide Memristor with Synaptic Plasticity. 1750161:1-1750161:17 - Atefeh Salimi, Rasoul Dehghani, Abdolreza Nabavi:
A Digital Linear-Switching Hybrid Power Amplifier for Envelope Tracking Hybrid Supply Modulators. 1750162:1-1750162:18 - Mohammad Babajanzadeh, Massoud Dousti:
Design of a Compact Dual-Mode Dual-Band Bandpass Filter Using Stacked-Loop Resonators Structure. 1750163:1-1750163:10 - Mostafa Parvizi, Abouzar Taghizadeh, Hamid Mahmoodian, Ziaddin Daei Koozehkanani:
A Low-Power Mixed-Mode SIMO Universal Gm-C Filter. 1750164:1-1750164:16 - Aleksei Tepljakov, Eduard Petlenkov, Emmanuel A. Gonzalez, Juri Belikov:
Digital Realization of Retuning Fractional-Order Controllers for an Existing Closed-Loop Control System. 1750165:1-1750165:26
Volume 26, Number 11, November 2017
- Haokun Chi, Yanping Cong, Zhiqiang Wei, Bo Yin, Feixiang Gong:
Influencing Factors of Inductance for 3D Micro-PCB Rectangular Coil. 1750166:1-1750166:17 - Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado:
CEPRAM: Compression for Endurance in PCM RAM. 1750167:1-1750167:32 - Javier Moreno-Valenzuela, Yajaira Quevedo-Pillado, Regino Pérez-Aboytes, Luis González-Hernández:
Lyapunov-Based Adaptive Control for the Permanent Magnet Synchronous Motor Driving a Robotic Load. 1750168:1-1750168:31 - Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti:
Fully Differential Class-AB OTA with Improved CMRR. 1750169:1-1750169:11 - Jerzy Baranowski, Pawel Piatek:
Fractional Band-Pass Filters: Design, Implementation and Application to EEG Signal Processing. 1750170:1-1750170:21 - Sudhanshu Maheshwari:
Realization of Simple Electronic Functions Using EXCCII. 1750171:1-1750171:12 - Fabian Khateb, Tomasz Kulej, Montree Kumngern, Vilem Kledrowetz:
Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier. 1750172:1-1750172:8 - Yuelong Li, Jigang Wu, Yawen Chen, Zhitao Xiao, Lei Geng, Fang Zhang, Jun Wu:
Is Correlation Ranking Really Reliable for the Performance Counter Selection Conducted for Power Estimation? 1750173:1-1750173:16 - Soumya J., K. Niranjan Babu, Santanu Chattopadhyay:
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture. 1750174:1-1750174:31 - Changyuan Chang, Chao Hong, Yang Xu, Hailong Sun, Yao Chen:
Design of a High-Precision Flyback Constant Voltage AC-DC Converter. 1750175:1-1750175:15 - Yani Li, Zhangming Zhu, Yintang Yang, Yadong Sun, Xu Wang:
A Novel Interface Circuit with 99.2% MPPT Accuracy and 1.3% THD for Energy Harvesting. 1750176:1-1750176:14 - Zhiming Yang, Yang Yu, Yue Guan, Chengcheng Zhang, Xiyuan Peng:
NBTI and Leakage Reduction Using an Integer Linear Programming Approach. 1750177:1-1750177:28 - Atif Raza Jafri, Muhammad Najam-ul-Islam, Malik Imran, Muhammad Rashid:
Towards an Optimized Architecture for Unified Binary Huff Curves. 1750178:1-1750178:14 - Goran S. Nikolic, Goran S. Jovanovic, Mile K. Stojcev, Tatjana R. Nikolic:
Precharged Phase Detector with Zero Dead-Zone and Minimal Blind-Zone. 1750179:1-1750179:16 - Leila Safari, Shahram Minaei:
A Low-Voltage Low-Power Resistor-Based Current Mirror and Its Applications. 1750180:1-1750180:18 - K. Madhan Kumar, A. Velayudham, R. Kanthavel:
An Efficient Method for Road Tracking from Satellite Images Using Hybrid Multi-Kernel Partial Least Square Analysis and Particle Filter. 1750181:1-1750181:30 - Indrit Myderrizi, Ali Zeki:
A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology. 1750182:1-1750182:14 - Rajeev Ranjan, Pablo Mendoza Ponce, Wolf Lukas Hellweg, Alexandros Kyrmanidis, Lait Abu Saleh, Dietmar Schroeder, Wolfgang H. Krautschneider:
Integrated Circuit with Memristor Emulator Array and Neuron Circuits for Biologically Inspired Neuromorphic Pattern Recognition. 1750183:1-1750183:19 - Qiuzhen Wan, Jun Dong, Hui Zhou, Fei Yu:
A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology. 1750184:1-1750184:13 - Mohammad Reza Mosavi, Mohammad Khishe:
Training a Feed-Forward Neural Network Using Particle Swarm Optimizer with Autonomous Groups for Sonar Target Classification. 1750185:1-1750185:20
Volume 26, Number 12, December 2017
- Sonia Afrooz, Nima Jafari Navimipour:
Memory Designing Using Quantum-Dot Cellular Automata: Systematic Literature Review, Classification and Current Trends. 1730004:1-1730004:34
- Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal:
New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies. 1750186:1-1750186:15 - Gianpiero Cabodi, Alessandro Garbo, Carmelo Loiacono, Stefano Quer, Gianluca Francini:
Efficient Complex High-Precision Computations on GPUs without Precision Loss. 1750187:1-1750187:38 - Sadiye Nergis Tural-Polat:
A Complete Embedded System Design of Breakout Game. 1750188:1-1750188:11 - Bibha Kumari, Nisha Gupta:
Realization of Chaotic Circuits Using Lambda Diode. 1750189:1-1750189:20 - Akif Akgul, Chunbiao Li, Ihsan Pehlivan:
Amplitude Control Analysis of a Four-Wing Chaotic Attractor, its Electronic Circuit Designs and Microcontroller-Based Random Number Generator. 1750190:1-1750190:20 - Majid Babaeinik, Massoud Dousti, Mohammad Bagher Tavakoli:
A High Bandwidth (DC-40 GHz) Pseudo Differential Distributed Amplifier in 0.18-μm RF CMOS. 1750191:1-1750191:9 - Jaroslav Koton, David Kubánek, Ondrej Sladok, Kamil Vrba, Aleksandr Shadrin, Peter Ushakov:
Fractional-Order Low- and High-Pass Filters Using UVCs. 1750192:1-1750192:23 - Xin Cheng, Hongyu Liang, Longjie Du, Zhang Zhang, Maoxiang Yi, Guangjun Xie:
An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator. 1750193:1-1750193:11 - Qunwei Xu, Dongdong Chen, Peng Xu, Guozhu Chen:
High Power Density Three-Phase Shunt Active Power Filter Design Based on Multiple Magnetic Integrations of LCL Filter. 1750194:1-1750194:22 - Yanzhao Ma, Yinghui Zou, Shengbing Zhang, Xiaoya Fan:
A 50 mV Fully-Integrated Self-Startup Circuit for Thermal Energy Harvesting. 1750196:1-1750196:12 - Fatemeh Abdi, Mahnaz Janipoor Deylamani, Parviz Amiri:
Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure. 1750197:1-1750197:17 - Abdelhakim Ridouh, Daoud Boutana, Salah Bourennane:
EEG Signals Classification Based on Time Frequency Analysis. 1750198:1-1750198:26 - Maedeh Fallahi, Abumoslem Jannesari:
A Low-Power Three-Tap DFE with Switched Resistor Slicer and CTLE in 0.18μm CMOS Technology. 1750199:1-1750199:14 - Ruilian Xie, Jueping Cai, Peng Wang, Xin Zhang, Juan Wang:
AFRM: Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip. 1750200:1-1750200:23 - Hamed Aminzadeh, Mohammad Ali Dashti, Mohammad Miralaei:
Nano-Scale Silicon Quantum Dot-Based Single-Electron Transistors and Their Application to Design of Analog-to-Digital Convertors at Room Temperature. 1750201:1-1750201:23 - Kirubakaran Annamalai:
Xilinx FPGA-Based Single Phase Seven-Level Inverter with Single Input DC Voltage Source. 1750202:1-1750202:20 - Ebrahim Babaei, Mohammad Shadnam Zarbil, Mehran Sabahi:
A New Structure of Quasi Z-Source-Based Cascaded Multilevel Inverter. 1750203:1-1750203:26 - S. Rashmi, Shankaraiah:
A Novel Faulty Phase Identification Algorithm and Fast DQ Transform Technique for Voltage Sag Detection. 1750204:1-1750204:17
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