"Multistage Latency Adders Architecture Employing Approximate Computing."

Xinghua Yang et al. (2017)

> Home

Details and statistics

DOI: 10.1142/S0218126617500396

access: closed

type: Journal Article

metadata version: 2023-09-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/YangXQY17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/YangXQY17
Xinghua Yang, Yue Xing, Fei Qiao, Huazhong Yang:
Multistage Latency Adders Architecture Employing Approximate Computing. J. Circuits Syst. Comput. 26(3): 1750039:1-1750039:18 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.