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ORCIDEdward Hrynkiewicz
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2010 – 2019
- 2017
[j3]Adam Milik
, Edward Hrynkiewicz:
Nonlinearity Measurement of a Voltage Ramp Using a Digital Technique. J. Circuits Syst. Comput. 26(5): 1750081:1-1750081:15 (2017)- 2016
- [j2]Bernard Wyrwol, Edward Hrynkiewicz:
Implementation of a microcontroller-based simplified FITA-FIS model. Microprocess. Microsystems 44: 22-27 (2016) - [c16]Dariusz Polok, Edward Hrynkiewicz:
About some peculiar approaches to seeking the Ashenhurst decomposition of logic functions in the Reed-Muller spectrum domain. MIXDES 2016: 155-159 - 2015
- [c15]Miroslaw Chmiel, Edward Hrynkiewicz, Dariusz Polok, Jan Mocha:
Popular microcontrollers execute IEC 61131-3 standard operators and functional blocks in simply automatic control tasks. MMAR 2015: 643-648 - 2014
- [c14]Blazej Kwiecien, Marcin Sidzina, Edward Hrynkiewicz:
Industrial Implementation of Failure Detection Algorithm in Communication System. CN 2014: 287-297 - [c13]Edward Hrynkiewicz, Dariusz Polok:
Seeking for decomposition of a Boolean function in the reed-müller spectral domain by Means of permutation between function variables. MIXDES 2014: 262-266 - 2013
- [j1]Bernard Wyrwol, Edward Hrynkiewicz:
Decomposition of the fuzzy inference system for implementation in the FPGA structure. Int. J. Appl. Math. Comput. Sci. 23(2): 473-483 (2013) - [c12]Danuta Pamula, Edward Hrynkiewicz:
Area-speed efficient modular architecture for GF(2m) multipliers dedicated for cryptographic applications. DDECS 2013: 30-35 - [c11]Miroslaw Chmiel, Jan Mocha, Edward Hrynkiewicz, Dariusz Polok:
About Implementation of IEC 61131-3 IL Operators in Standard Microcontrollers. PDeS 2013: 144-149 - 2012
- [c10]Miroslaw Chmiel, Edward Hrynkiewicz:
The dynamic properties investigation of the PLC CPU implemented in FPGA. PDeS 2012: 151-156 - [c9]Danuta Pamula, Edward Hrynkiewicz, Arnaud Tisserand:
Analysis of GF (2233) multipliers regarding elliptic curve cryptosystem applications. PDeS 2012: 271-276 - 2011
- [c8]Stefan Kolodzinski, Edward Hrynkiewicz:
Decomposition of multi-output logic function in Reed-Muller spectral domain. DDECS 2011: 179-182 - 2010
- [c7]Edward Hrynkiewicz, Stefan Kolodzinski:
Non-disjoint decomposition of logic functions in Reed-Muller spectral domain. DDECS 2010: 293-296 - [c6]Danuta Pamula, Edward Hrynkiewicz, Arnaud Tisserand:
Multiplication in GF(2m): Area and time dependency/efficiency/complexity analysis. PDeS 2010: 28-33 - [c5]Miroslaw Chmiel, Jan Mocha, Edward Hrynkiewicz:
A FPGA-based bit-word PLC CPUs development platform. PDeS 2010: 132-137 - [e1]Adam Milik, Edward Hrynkiewicz:
10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010, Gliwice, Poland, October 6-7, 2010. International Federation of Automatic Control 2010, ISBN 978-3-902661-95-1 [contents]
2000 – 2009
- 2009
- [c4]Stefan Kolodzinski, Edward Hrynkiewicz:
An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions. DDECS 2009: 34-37 - [c3]Miroslaw Chmiel, Edward Hrynkiewicz:
An idea of event-driven program tasks execution. PDeS 2009: 17-22 - 2007
- [c2]Maciej Witczynski, Edward Hrynkiewicz, Adam Pawlak:
A Web Services based Approach for System on a Chip Design Planning. CCE 2007: 61-71 - [c1]Edward Hrynkiewicz, Stefan Kolodzinski:
Decomposition of Logic Functions in Reed-Muller Spectral Domain. DDECS 2007: 219-222
Coauthor Index
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