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"Area-speed efficient modular architecture for GF(2m) ..."

Danuta Pamula, Edward Hrynkiewicz (2013)

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DOI: 10.1109/DDECS.2013.6549784

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  persistent URL:
  - https://dblp.org/rec/conf/ddecs/PamulaH13
Danuta Pamula, Edward Hrynkiewicz:
Area-speed efficient modular architecture for GF(2^m) multipliers dedicated for cryptographic applications. DDECS 2013: 30-35

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