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Jiri Jenícek
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2020 – today
- 2020
- [c18]Tomás Jakubík, Jiri Jenícek:
Feasibility of OFDM and FHSS in a Single Home Automation and Security Network. TSP 2020: 19-22
2010 – 2019
- 2019
- [c17]Tomás Jakubík, Jiri Jenícek:
SDR All-channels Receiver for FHSS Sensor Network in Cortex-M. TSP 2019: 32-35 - 2017
- [j1]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Sequential Test Decompressors with Fast Tester Bits Wide-Spreading. J. Circuits Syst. Comput. 26(8): 1740001:1-1740001:16 (2017) - 2016
- [c16]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Sequential test decompressors with fast variable wide spreading. DDECS 2016: 132-137 - [c15]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test Decompressor Effectivity Improvement. DSD 2016: 661-664 - 2015
- [c14]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs. DDECS 2015: 9-14 - [c13]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test compression for circuits with multiple scan chains. LATS 2015: 1-6 - 2014
- [c12]Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Test-data compression with low number of channels and short test time. DDECS 2014: 104-109 - 2013
- [c11]Martin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec:
Test pattern decompression in parallel scan chain architecture. DDECS 2013: 219-223 - 2012
- [c10]Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
An evaluation of the application dependent FPGA test method. DDECS 2012: 22-25 - [c9]Martin Chloupek, Ondrej Novák, Jiri Jenícek:
On test time reduction using pattern overlapping, broadcasting and on-chip decompression. DDECS 2012: 300-305 - 2011
- [c8]Jiri Jenícek, Martin Rozkovec, Ondrej Novák:
Test vector overlapping based compression tool for narrow test access mechanism. DDECS 2011: 387-392 - [c7]Jiri Jenícek, Ondrej Novák, Martin Chloupek:
Advanced scan chain configuration method for broadcast decompressor architecture. EWDTS 2011: 140-143 - 2010
- [c6]Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
Application Dependent FPGA Testing Method. DSD 2010: 525-530 - [c5]Jiri Jenícek, Ondrej Novák:
COMPAS - Advanced test compressor. EWDTS 2010: 543-548 - [c4]Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
Application dependent FPGA testing method using compressed deterministic test vectors. IOLTS 2010: 192-193
2000 – 2009
- 2008
- [c3]Jiri Jenícek:
Efficient Test Pattern Compression Method Using Hard Fault Preferring. DSD 2008: 703-708 - 2007
- [c2]Jiri Jenícek, Ondrej Novák:
Test Pattern Compression Based on Pattern Overlapping. DDECS 2007: 29-34 - 2006
- [c1]Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský:
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. DFT 2006: 300-308
Coauthor Index
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