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ORCIDAlpana Agarwal
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2020 – today
- 2024
[j18]Naveen Kandpal
, Anil Singh, Alpana Agarwal:
An artificial intelligence-based 4-to-10-bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate. Int. J. Circuit Theory Appl. 52(8): 4067-4085 (2024)- [j17]Abhishek Mishra, Anil Singh, Alpana Agarwal:
Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology. J. Circuits Syst. Comput. 33(8) (2024) - 2022
- [j16]Amandeep Kaur, Sanjay Kumar, Ravinder Agarwal, Alpana Agarwal:
Intra and inter-patient arrhythmia classification using feature fusion with novel feature set based on fractional-order and fibonacci series. Biomed. Signal Process. Control. 72(Part): 103365 (2022) - [j15]Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. Circuits Syst. Signal Process. 41(3): 1299-1323 (2022) - [j14]Naveen Kandpal, Anil Singh, Alpana Agarwal:
A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity Range. Circuits Syst. Signal Process. 41(8): 4275-4292 (2022) - [j13]Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. Int. J. Circuit Theory Appl. 50(8): 2900-2912 (2022) - [j12]Ashima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal:
Functional validation of highly synthesizable voltage comparator on FPGA. Integr. 84: 151-158 (2022) - [j11]Ashima Gupta, Anil Singh, Alpana Agarwal:
A Scalable Fully-Digital Differential Analog Voltage Comparator. J. Circuits Syst. Comput. 31(4): 2250059:1-2250059:25 (2022) - 2021
- [j10]Shivani Malhotra, Vinay Kumar, Alpana Agarwal:
Bidirectional transfer learning model for sentiment analysis of natural language. J. Ambient Intell. Humaniz. Comput. 12(11): 10267-10287 (2021) - [i1]Shivani Malhotra, Vinay Kumar, Alpana Agarwal:
Entropy optimized semi-supervised decomposed vector-quantized variational autoencoder model based on transfer learning for multiclass text classification and generation. CoRR abs/2111.08453 (2021) - 2020
- [j9]Amandeep Kaur, Sanjay Kumar, Alpana Agarwal, Ravinder Agarwal:
An Efficient R-Peak Detection Using Riesz Fractional-Order Digital Differentiator. Circuits Syst. Signal Process. 39(4): 1965-1987 (2020) - [j8]Ashima Gupta, Anil Singh, Alpana Agarwal:
Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC. J. Circuits Syst. Comput. 29(5): 2050073:1-2050073:21 (2020) - [j7]Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology. J. Circuits Syst. Comput. 29(8): 2050130:1-2050130:15 (2020) - [j6]Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology. J. Circuits Syst. Comput. 29(9): 2050142:1-2050142:22 (2020)
2010 – 2019
- 2019
- [j5]Ashima Gupta, Anil Singh, Alpana Agarwal:
Highly-digital voltage scalable 4-bit flash ADC. IET Circuits Devices Syst. 13(1): 91-97 (2019) - [j4]Jupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal:
Fast digital foreground gain error calibration for pipelined ADC. IET Circuits Devices Syst. 13(2): 219-225 (2019) - [c4]Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. IntelliSys (1) 2019: 266-275 - 2017
- [j3]Anil Singh, Veena Rawat, Alpana Agarwal:
Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technology. IET Circuits Devices Syst. 11(6): 589-596 (2017) - [j2]Anil Singh, Ayushi Goel, Alpana Agarwal:
A Digital-Based Low-Power Fully Differential Comparator. J. Circuits Syst. Comput. 26(1): 1750002:1-1750002:12 (2017) - 2013
- [c3]Madhusoodan Agrawal, Alpana Agarwal:
A Combined CMOS Reference Circuit with Supply and Temperature Compensation. VDAT 2013: 177-184 - 2011
- [c2]Alpana Agarwal, Chandra Shekhar:
Synthesis of Analog IC Building Blocks. ISVLSI 2011: 361-362
2000 – 2009
- 2008
- [j1]Alpana Agarwal, Chandra Shekhar:
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers. VLSI Design 2008: 847932:1-847932:5 (2008) - 2004
- [c1]Varun Jindal, Alpana Agarwal:
Carry Circuitry for LUT-Based FPGA. VLSI Design 2004: 731-734
Coauthor Index
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