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ORCIDChandra Shekhar 0001
Person information
- affiliation: Central Electronics Engineering Research Institute (CEERI), Pilani, India
Other persons with the same name
- Chandra Shekhar 0002 — University of Maryland, College Park, USA
- Chandra Shekhar 0003 — Birla Institute of Technology and Science, Department of Mathematics, Pilani, India
- Chandra Shekhar 0004
![[0000-0002-6288-9971]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-6288-9971")
— Indian Institute of Information Technology Allahabad, Department of Electronics and Communication Engineering, India - Chandra Shekhar 0005 — Yokohama National University, Department of Mechanical Engineering, Japan
- Chandra Shekhar 0006 — Indian Institute of Technology Kanpur, Department of Electrical Engineering, India
- Chandra Shekhar 0007 — IIT Bhubaneswar, India
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2020 – today
- 2022
[j12]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. Wirel. Pers. Commun. 127(3): 1869-1878 (2022)- 2021
- [j11]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. Comput. Intell. 37(3): 1056-1067 (2021) - [j10]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. Circuits Syst. Signal Process. 40(6): 2883-2894 (2021) - [j9]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. Microprocess. Microsystems 80: 103514 (2021) - 2020
- [j8]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
High-Level synthesis assisted design and verification framework for automotive radar processors. Microprocess. Microsystems 78: 103259 (2020) - [j7]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Speed optimal FPGA implementation of the encryption algorithms for telecom applications. Microprocess. Microsystems 79: 103324 (2020)
2010 – 2019
- 2019
- [j6]Gaurav Purohit, Divya Vyas, Vinod Kumar Chaubey, Kota Solomon Raju, Chandra Shekhar:
A New XOR-FREE Approach to Implement Walsh Sequences. Wirel. Pers. Commun. 109(1): 51-60 (2019) - 2017
- [j5]Sanjay Singh, Chandra Shekhar, Anil Vohra:
Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems. J. Imaging 3(2): 18 (2017) - [j4]Sanjay Singh, Atanendu Sekhar Mandal, Chandra Shekhar, Anil Vohra:
Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform. J. Imaging 3(2): 20 (2017) - 2015
- [c17]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. VDAT 2015: 1-6 - [c16]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. VLSID 2015: 339-344 - 2014
- [c15]Sanjay Singh, Sumeet Saurav, Ravi Saini, Anil K. Saini, Chandra Shekhar, Anil Vohra:
Automatic real-time extraction of focused regions in a live video stream using edge width information. VDAT 2014: 1-2 - [c14]Sanjay Singh, Ravi Saini, Sumeet Saurav, Anil K. Saini, Chandra Shekhar, Anil Vohra:
FPGA-based real-time object tracker using modified particle filtering and SAD computation. VDAT 2014: 1-2 - [c13]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. VLSID 2014: 300-305 - 2011
- [c12]Alpana Agarwal, Chandra Shekhar:
Synthesis of Analog IC Building Blocks. ISVLSI 2011: 361-362 - 2010
- [j3]Subhendu Kumar Sahoo, Anu Gupta, Abhijit R. Asati, Chandra Shekhar:
A Novel Redundant Binary Number to Natural Binary Number Converter. J. Signal Process. Syst. 59(3): 297-307 (2010) - [c11]Sanjay Singh, Srinivasa Murali Dunga, Atanendu S. Mandal, Chandra Shekhar, Anil Vohra:
Moving Object Tracking Using Object Segmentation. ICT 2010: 691-694
2000 – 2009
- 2009
- [j2]Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta:
Dual channel addition based FFT processor architecture for signal and image processing. Int. J. High Perform. Syst. Archit. 2(1): 35-45 (2009) - [c10]Abhijit R. Asati, Subhendu Kumar Sahoo, Chandra Shekhar:
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load. ICETET 2009: 121-124 - 2008
- [j1]Alpana Agarwal, Chandra Shekhar:
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers. VLSI Design 2008: 847932:1-847932:5 (2008) - [c9]Subhendu Kumar Sahoo, Abhijit Ashati, Rasmita Sahoo, Chandra Shekhar:
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic. ICETET 2008: 474-479 - 2005
- [c8]A. Madan, S. C. Bose, P. J. George, Chandra Shekhar:
Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. VLSI Design 2005: 386-391 - 2004
- [c7]Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh, Chandra Shekhar:
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. VLSI Design 2004: 773-775 - [c6]Chandra Shekhar, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini, Pramod Tanwar:
Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary. VLSI Design 2004: 915- - 2001
- [c5]B. Prasad, P. J. George, Chandra Shekhar:
High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors. VLSI Design 2001: 491-494
1990 – 1999
- 1998
- [c4]S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar, Sudhir Kumar, Amit K. Agarwal:
Evolution of Architectural Concepts and Design Methods of Microprocessors. VLSI Design 1998: 312-317 - 1992
- [c3]Chandra Shekhar, A. S. Mandal:
Design of an Efficient ASIC for the Control of Microwave Ovens. VLSI Design 1992: 293-296 - [c2]K. V. S. H. Rao, A. Kansal, Chandra Shekhar, M. Srinivas, V. N. S. N. Rao:
An ASIC for High Performance Stepper Motor Control. VLSI Design 1992: 328-329 - [c1]K. V. S. H. Rao, Raj Singh, Chandra Shekhar:
Using Dedicated Functional Simulator for ASIC Design in Indian Context. VLSI Design 1992: 334-335
Coauthor Index
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