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2020 – today
- 2022
[j7]Prateek Sikka
:
Hashed Access Policy-Based Secure Data Transmission Using SDHAK-ECC. Int. J. Cooperative Inf. Syst. 31(3&4): 2350001:1-2350001:21 (2022)- [j6]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. Wirel. Pers. Commun. 127(3): 1869-1878 (2022) - 2021
- [j5]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. Comput. Intell. 37(3): 1056-1067 (2021) - [j4]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. Circuits Syst. Signal Process. 40(6): 2883-2894 (2021) - [j3]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. Microprocess. Microsystems 80: 103514 (2021) - 2020
- [j2]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
High-Level synthesis assisted design and verification framework for automotive radar processors. Microprocess. Microsystems 78: 103259 (2020) - [j1]Prateek Sikka, Abhijit R. Asati, Chandra Shekhar:
Speed optimal FPGA implementation of the encryption algorithms for telecom applications. Microprocess. Microsystems 79: 103324 (2020)
2010 – 2019
- 2018
- [c1]Sujoy Pandit, Prateek Sikka:
Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA. ICCCNT 2018: 1-5
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