default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 84
Volume 84, May 2022
- Rongjin Xu
, Dawei Ye, Chuanjin Richard Shi:
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. 1-11 - Venkata Krishna Odugu, C. Venkata Narasimhulu, K. Satya Prasad:
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers. 12-25 - Ankur Gogoi, Bibhas Ghoshal, Akash Sachan, Rakesh Kumar, Kanchan Manna:
Application driven routing for mesh based Network-on-Chip architectures. 26-36 - S. Skandha Deepsita, Sk. Noor Mahammad:
Low power, high speed approximate multiplier for error resilient applications. 37-46 - Mihika Mahendra, Shweta Kumari, Maneesha Gupta:
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application. 47-61 - Naveen Kumar Macha, Md Arif Iqbal, Bhavana Tejaswini Repalle, Mostafizur Rahman:
On circuit developments to enable large scale circuit design while computing with noise. 62-71 - Javad Ahsan, Mohammad Esmaeildoust, Amer Kaabi, Vahid Zarei:
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases. 72-83
- Xiang He, Zhufei Chu:
Stochastic circuit synthesis via satisfiability. 84-91
- Manas Parai, Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman:
Multi-source data fusion technique for parametric fault diagnosis in analog circuits. 92-101 - Farshad Aghasharif, Mohammadreza Malekpour, Reza Bigdeli, Pooya Torkzadeh:
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration. 102-110 - Mohamed B. Elamien, Brent J. Maundy, Ahmed S. Elwakil, Leonid Belostotski:
Second-order cascode-based filters. 111-121 - Mohamed Chentouf, Zine El Abidine Alaoui Ismaili:
A PUS based nets weighting mechanism for power, hold, and setup timing optimization. 122-130 - David C. C. Freitas, Jarbas Silveira, César A. M. Marcon, Lirida A. B. Naviner, João Cesar M. Mota:
OPCoSA: an Optimized Product Code for space applications. 131-141
- Arnau Salas Barenys, Neus Vidal, José María López-Villegas:
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines. 142-150
- Ashima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal:
Functional validation of highly synthesizable voltage comparator on FPGA. 151-158
- Alejandro Suanes, Michele Dei, Lluís Terés, Francisco Serra-Graells:
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs. 159-170 - Jose Angel Miranda, Manuel Felipe Canabal, Laura Gutiérrez-Martín, José Manuel Lanza-Gutiérrez, Celia López-Ongil:
Edge computing design space exploration for heart rate monitoring. 171-179
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-05 21:06 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
