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ORCIDMohamed Chentouf
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2020 – today
- 2024
[j6]Yassine Attaoui
, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit:
Enhancing cell delay accuracy in post-placed netlists using ensemble tree-based algorithms. Integr. 97: 102193 (2024)- 2023
- [j5]Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit:
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells. Integr. 90: 261-270 (2023) - 2022
- [j4]Mohamed Chentouf, Zine El Abidine Alaoui Ismaili:
A PUS based nets weighting mechanism for power, hold, and setup timing optimization. Integr. 84: 122-130 (2022) - 2021
- [j3]Mohamed Chentouf, Foffie Stevmelin, Zine El Abidine Alaoui Ismaili:
Power-aware hold optimization for ASIC physical synthesis. Integr. 76: 13-24 (2021) - [c5]Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit:
A new MBFF merging strategy for post-placement power optimization of IoT devices. AICCSA 2021: 1-6 - [c4]Mohamed Chentouf, Zine El Abidine Alaoui Ismaili:
A New Leakage Optimization Approach for IoTs Physical Design. AICCSA 2021: 1-8 - [c3]Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit:
Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow. ICM 2021: 13-16 - [c2]Mohamed Chentouf, Chaimaa Naimy, Zine El Abidine Alaoui Ismaili:
Machine Learning Application for Early Power Analysis Accuracy Improvement: A Case Study for Cells Switching Power. ICM 2021: 17-20
2010 – 2019
- 2019
- [j2]Mohamed Chentouf, Soukaina Mourssi, Zine El Abidine Alaoui Ismaili:
Power aware setup timing optimization in physical design of ASICs. Microelectron. J. 83: 147-154 (2019) - 2018
- [j1]Mohamed Chentouf, Zine El Abidine Alaoui Ismaili:
A Novel Net Weighting Algorithm for Power and Timing-Driven Placement. VLSI Design 2018: 3905967:1-3905967:9 (2018) - [c1]Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri, Nabil Hmina:
Layer Optimization for Power Reduction in Integrated Circuits. CIST 2018: 625-629
Coauthor Index
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