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ORCIDKirti Gupta
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j25]Aditi Chauhan, Yashika Kukkar, Preeti Nagrath, Kirti Gupta, D. Jude Hemanth:
Integrating LSTM and NLP techniques for essay generation. Intell. Decis. Technol. 18(1): 571-584 (2024)- [j24]Kirti Gupta
, Bijaya Ketan Panigrahi, Anupam Joshi, Kolin Paul:
Demonstration of denial of charging attack on electric vehicle charging infrastructure and its consequences. Int. J. Crit. Infrastructure Prot. 46: 100693 (2024) - [j23]Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi:
Delay-Aware Semantic Sampling in Power Electronic Systems. IEEE Trans. Smart Grid 15(4): 4038-4049 (2024) - [j22]Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi:
A Monolithic Cybersecurity Architecture for Power Electronic Systems. IEEE Trans. Smart Grid 15(4): 4217-4227 (2024) - [i3]Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi:
Delay-Aware Semantic Sampling in Power Electronic Systems. CoRR abs/2402.13586 (2024) - [i2]Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi:
A Monolithic Cybersecurity Architecture for Power Electronic Systems. CoRR abs/2402.13617 (2024) - 2023
- [j21]Shikha, Neeta Pandey, Kirti Gupta:
Memristor-Based Architectures for PFSCL Circuit Realizations. Circuits Syst. Signal Process. 42(8): 4985-5012 (2023) - [j20]Damyanti Singh, Neeta Pandey, Kirti Gupta:
Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell. Microelectron. J. 135: 105773 (2023) - [i1]Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi, Charalambos Konstantinou:
Impact Assessment of Data Integrity Attacks in MVDC Shipboard Power Systems. CoRR abs/2305.19778 (2023) - 2022
- [j19]Ranjana Sivaram, Kirti Gupta, Neeta Pandey:
On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates. Microprocess. Microsystems 90: 104521 (2022) - [j18]Damyanti Singh, Kirti Gupta, Neeta Pandey:
A novel read decoupled 8T1M nvSRAM cell for near threshold operation. Microelectron. J. 126: 105496 (2022) - [c5]Aniket Kumar, Mehul Madaan, Shubham Kumar, Aniket Saha, Kirti Gupta:
Handwriting Generation and Synthesis using Recurrent Neural Networks. ICCCNT 2022: 1-8 - [c4]Kirti Gupta, Parul Goyal:
Test Suites Generation using UML Modelling and Heuristic Techniques: A Systematic Study. ICIMMI 2022: 58:1-58:11 - 2021
- [j17]Georgios Effraimidis, Kirti Gupta, Urka Petrovcic:
Was the Update of the 2015 Business Review Letter to the IEEE Justified? IEEE Commun. Stand. Mag. 5(4): 129-139 (2021) - [j16]Monica Gupta, Kirti Gupta, Neeta Pandey:
A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region. Int. J. Circuit Theory Appl. 49(4): 953-969 (2021) - [j15]Monica Gupta, Kirti Gupta, Neeta Pandey:
A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. Int. J. Circuit Theory Appl. 49(11): 3789-3810 (2021) - [j14]Monica Gupta, Kirti Gupta, Neeta Pandey:
Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm. Microprocess. Microsystems 85: 104281 (2021) - 2020
- [b1]Kirti Gupta, Neeta Pandey, Maneesha Gupta:
Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended. Springer 2020, ISBN 978-981-15-0981-0, pp. 1-171 - [j13]Ranjana Sivaram, Kirti Gupta, Neeta Pandey:
A new realization scheme for dynamic PFSCL style. Integr. 75: 169-177 (2020) - [j12]Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey:
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. Microelectron. J. 97: 104703 (2020)
2010 – 2019
- 2019
- [j11]Shourya Gupta, Kirti Gupta, Benton H. Calhoun, Neeta Pandey:
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 978-988 (2019) - 2018
- [j10]Shourya Gupta, Kirti Gupta, Neeta Pandey:
Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3326-3337 (2018) - [c3]Neeta Pandey, Kirti Gupta, Bharat Choudhary:
MCML Dynamic Register Design. MWSCAS 2018: 582-586 - 2017
- [j9]Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal:
New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies. J. Circuits Syst. Comput. 26(12): 1750186:1-1750186:15 (2017) - [j8]Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda:
On Improving the Performance of Dynamic DCVSL Circuits. J. Electr. Comput. Eng. 2017: 8207104:1-8207104:11 (2017) - [j7]Shourya Gupta, Kirti Gupta, Neeta Pandey:
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3473-3483 (2017) - [c2]Naman Saxena, Shruti Dutta, Neeta Pandey, Kirti Gupta:
Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies. ICCSA (6) 2017: 299-313 - 2016
- [j6]Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary:
MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells. Microelectron. J. 57: 13-20 (2016) - [j5]Neeta Pandey, Kirti Gupta, Bharat Choudhary:
New Proposal for MCML Based Three-Input Logic Implementation. VLSI Design 2016: 8712768:1-8712768:10 (2016) - [c1]Shobhit Kareer, Anchit Kumar, Kirti Gupta, Neeta Pandey:
A Novel Bulk Drain Connected 6T SRAM Cell. ICACDS 2016: 232-242 - 2015
- [j4]Kirti Gupta, Rashmi Gupta:
Multi-resolution wavelet-based image fusion for iris recognition. Int. J. Appl. Pattern Recognit. 2(2): 182-198 (2015) - 2014
- [j3]Neeta Pandey, Kirti Gupta, Maneesha Gupta:
An efficient triple-tail cell based PFSCL D latch. Microelectron. J. 45(8): 1001-1007 (2014) - 2013
- [j2]Kirti Gupta, Neeta Pandey, Maneesha Gupta:
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. Microelectron. J. 44(6): 561-567 (2013) - 2011
- [j1]Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta:
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic. J. Electr. Comput. Eng. 2011: 670508:1-670508:6 (2011)
Coauthor Index
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